Welcome and Introduction: Peter N.
Glaskowsky, Editor in Chief of Microprocessor Report, In-Stat/MDR
Keynote Address: Chekib Akrout, VP of PPC and Networking Technology
Development, IBM Microelectronics
Presented by: Markus Levy
First Details of AMBA 3.0
ARM, Bruce Mathewson,
SoC Design Centre Manager
This presentation will deliver
the first public disclosure of the AMBA 3.0 Interconnect Specification.
AMBA 3.0 implements a channel-based architecture, an out-of-order
completion model, and includes optional extensions for data
request signaling.
New Extensions to the ARM v6 Architecture
ARM, Vladimir Vasekin,
CPU Architect
This presentation builds
on the previously announced details of the ARM v6 architecture,
focusing on new 16- and 32-bit Thumb instructions designed
for great compiler flexibility and analyzed with the assistance
of EEMBC benchmark suites. The presentation also includes
details of new 32-bit instructions for data processing and
load/store operations.
A New 32-Bit High-Performance MIPS Microarchitecture
MIPS Technologies,
Inc., Michael Uhler, CTO
MIPS Technologies will be
announcing the first public details of a new, deeply-pipelined,
microarchitecture designed for higher frequency operation
than any other synthesizable microprocessor IP.
GNU Support for 8-Way SIMD Instructions
in SH-5
SuperH, Andy Sturges,
Director of IP
This will be SuperH's first
public disclosure on GNU vector extensions for the SH-5 architecture,
demonstrating a trend in a compiler's ability to utilize SIMD
instructions. The presentation will also discuss the basics
of SIMD implementation for SuperH's next generation SH-6 architecture.
Tools to Generate Extensions for Tensilica's
FLIX and SIMD
Tensilica, Inc.,
Dror Maydan, Director of Software Development
Tensilica will present the
technical advances of instruction set generation, vectorization,
scheduling, operator fusion, and VLIW, used to generate processor
extensions for FLIX and SIMD instructions.
Speed Path Enhancements for TI's C64x
Texas Instruments,
Ray Simar, Manager, DSP Advanced Architecture Development
This presentation will explore
critical speed paths of the TI C6x architecture and its most
recent implementation embodied in the C64x, providing the
distribution of critical speed paths within the design, as
well as implementation details for the design and the partitioning
between synthesized logic and custom logic.
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Presented by: Max Baron
An Advanced Power Management Architecture
for Embedded Microprocessors
National Semiconductor,
Juha Pennanen, Systems Applications Engineer
National will unveil the
architecture details and review performance data for its closed-loop
adaptive voltage scaling technology. National will also announce
at EPF 2003 the availability of open interface specifications
for voltage control enabling energy savings in systems-on-chip
designs.
Intelligent Energy Management Technology
ARM, Krisztian
Flautner, Principal Research Engineer
Mr. Flautner will describe
software-managed run-time algorithms that can automatically
reduce systems power comsumption to the minimum required for
the tasks at hand. This functionality is enabled by SoCs that
support dynamic scaling of multiple voltage and frequency
domains.
A Multithreading Extension for Low-Power,
Low-Cost Applications
Infineon Technologies,
Erik Norden, Senior Architect
Infineon will present a
block multithreading architecture extension that responds
to blocking code memory latency in one thread by executing
the instructions of a second thread. The architecture can
use smaller caches and slower external memory to deliver power-efficient
performance.
A Low-Power, High-Performance Processor
for Mobile Multimedia
NeoMagic Corporation,
Sanjay Adkar, VP of Corporate Engineering
NeoMagic will present a new
low-power applications processor augmented by an associative
processing array that targets complex multimedia tasks by
employing a novel high-performance architecture that helps
reduce power requirements.
A Low-Power Direct Execution Java
Microcontroller
Octera, Laurence
Flora, President
Octera will present the company's
low-power direct execution JVM processor that can execute
the most frequent bytecodes in a single cycle leading to a
high-performance rating per MHz and to power savings by comparison
with general-purpose processors.
Additional panelists: Sheila Rader,
Distinguished Member of the Technical Staff, Motorola &
Tom Adelmeyer, XScale Lead Architect, Intel
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- Sponsored by: MIPS Technologies
“The Death of the DSP?”
Moderator: Peter
Glaskowsky, Principal Analyst, In-Stat/MDR Sponsored by: MIPS
Technologies
MIPS Technologies and In-Stat/MDR
analysts will host an EPF panel debate on a controversial
topic of interest to followers of the embedded-processor industry.
Featuring recognized DSP and microprocessor visionaries, the
debate will explore the future of multimedia and digital signal
processing. With SOC economics changing rapidly from advances
in software and semiconductor process technology, there is
considerable disagreement whether the future of signal processing
will belong to custom hardwired logic elements, special-purpose
DSPs, reprogrammable-logic devices, or enhanced general-purpose
microprocessors. As in last year's standing-room-only event,
attendees will be welcomed to challenge the panelists with
their viewpoints and opinions.
Panelists: Jeff Bier, General Manager,
BDTI; Will Strauss, Founder and Principal Analyst, Forward
Concepts; Taun Dao, Vice President of the DSP products division,
LSI; Tom Riordan, Vice President and General Manager, MIPS
Business Unit, PMC-Sierra; Ray Simar, Senior Fellow, Texas
Instruments; Nick Tredennick, Independent Analyst; Jim Turley,
Independent Analyst
Welcome and Introduction: Peter N.
Glaskowsky, Editor in Chief of Microprocessor Report, In-Stat/MDR
Keynote Address: Dr. Claudine Simson, Corporate Vice President
and Chief Technology Officer, Motorola's Semiconductor Products
Sector
Presented by: Tom R. Halfhill
A High-Performance DSP with Embedded DRAM
Analog Devices Inc.,
Kevin Leary, Product Line Director; co-authored by Steve Tomashot, IBM
A VLIW Broadband Signal Processor
Equator Technologies, John Setel O'Donnell, Co-Founder and
CTO
Equator Technologies will
unveil its next-generation processor for consumer digital
media players and recorders. This highly integrated device
is adaptable to multiple industry compression standards and
is programmable in C and C++.
A Reconfigurable Algorithm Processor
Integrated with Toshiba's MeP
Elixent Ltd., Alan Marshall, CTO; co-authored by Hiroyuki Takano, Toshiba SoC R&D Center
This will be the first public
disclosure of a new chip that integrates a reconfigurable
array with Toshiba's MeP configurable processor core. Toshiba
is contributing to the presentation, which will describe the
chip's architecture and dynamically reconfigurable technology.
A Reconfigurable-Fabric Signal Processor
Motorola, Inc., Roman Robles, Manager, Digital Technologies
Operation
This will be the first full
public disclosure of the first chip from Motorola to use a
reconfigurable compute fabric. It's designed to be a programmable
alternative to ASICs for compute-intensive tasks, such as
WCDMA baseband signal processing, echo cancellation, and video
processing.
A Massively Parallel Array Processor
picoChip, Pete Claydon, Founder, Chief Architect and COO
picoChip's new PC101 integrates
more than 400 heterogeneous 16-bit processors on a single
die. The processor arrays have enough redundancy to tolerate
some defective elements during manufacture. picoChip will
describe the architecture, on-chip interconnects, and parallel-processing
development tools.
Special Presentation: Business Forecast
Christie Van Gaal, Sr. Director of Content Development, In-Stat
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Presented by: Peter N. Glaskowsky
A Flow-Through Storage Security Processor
Hifn, Scott Finley, Director of Technical Marketing
Hifn
will disclose the first technical details of its new HIPP
III 4300 Storage Security Processor, the company's first security
processor designed for IP storage networks. This chip can
secure multi-gigabit storage networks based on the iSCSI and
FCIP standards. The chip also addresses the IPSec requirements
of the Network Attached Storage (NAS) market.
CCP: A Customizable Control Processor
IBM Corporation, Santosh Gaur, Senior Technical Staff Member
IBM will announce its first
Customizable Control Processor (CCP), a PPC405-based chip
with various peripherals using the CoreConnect bus in 130nm
process technology. IBM will also describe the CCP product
roadmap with more speed and additional cores from IBM and
third parties.
A Multithreaded Wireless Network Processor
with Software I/O
Ubicom, Inc., David Fotland, CTO
Ubicom will discuss the
technical details of its new IP3023 wireless network processor,
showing how techniques like determinism, multithreading and
a memory-to-memory instruction set have enabled high performance
software I/O. The presentation will describe how these techniques
address the unique requirements of packet processing, resulting
in significantly reduced silicon area and better performance.
Two New WinPath Processors for the Access
Market
Wintegra, Yoram Yeivin, Vice President, Engineering
Wintegra will announce two
new Access Packet Processors from its WinPath family. The
first is the company's new processor for networking and communications
applications with more network interfaces. In addition the
company will also disclose a new family member for multi-service
applications.
Panel: Breaking the Barriers of Embedded
System Designs
Moderated by Markus Levy, In-Stat/MDR
This panel discussion includes
participants with a wide variety of backgrounds including
compilers, operating systems, processor architectures, and
memory and I/O subsystems. Panelists will use this background
to explore topics such as development of compiler technology
for advanced architectures, dealing with performance bottlenecks
of processor architectures and microarchitectures, supporting
multiprocessing and multithreading techniques, and the evolution
of system-level issues including memory bandwidth and next
generation I/O interfaces.
Panelists: Berardino Baratta, Metrowerks; Tom Petersen,
MIPS Technologies; Wilco Dijkstra, ARM; Sebastien Marineau,
QNX; Victor Menasce, Tundra; Tom Riordan, PMC Sierra.
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