8:30 am: Special
Presentation: Extreme Ultraviolet Lithography for Next Generation IC's
Charles
W. Gwyn - Program Director, Intel Corporation & EUV LLC
The impending
limits of conventional optical lithography require a revolutionary
approach to fabricate IC's with ever-smaller features as described
by Moore's Law. Extreme ultraviolet (EUV) lithography uses a very
short wavelength light for the exposure process. This technology development
by an industry led consortium is nearing completion and the technology
is being transferred to commercial manufacturers. EUV lithography
is expected to support IC production starting in 2005 with 70 nm features
and extending down to less than 30 nm features and perhaps to the
end of conventional silicon scaling as presently practiced.
8:55 am: Panel
and Demo: The 3D Millennium
Peter
Glaskowsky, senior analyst for 3D and multimedia technology; senior
editor, Microprocessor Report, MicroDesign Resources
Join moderator
Peter Glaskowsky, senior editor of the Microprocessor Report, and
representatives of major 3D-hardware companies as they demonstrate
and discuss the state of the art in computer graphics. The panelists
will also explore the future of 3D in applications ranging from wristwatches
to the PC to video walls.
Session
4
9:40 am
Information
Appliance Processors
Moderators: Markus
Levy, Senior Analyst and Senior Editor Microprocessor Report,
MicroDesign Resources and Cary
Snyder, Senior Analyst and Senior Editor Microprocessor Report,
MicroDesign Resources
The coming era of
the information appliance has sparked an explosion in processor development.
Many architectures compete in this arena where instruction-set compatibility
is not nearly as important as cost, performance, and power dissipation.
ARM
Media Extensions
John
Rayfield - Director of Technical Marketing, ARM Ltd.
This presentation
provides a first, detailed look at instruction set extensions, including
SIMD operations, developed by ARM for media-intense processing applications
such as video coding. Particular attention will be paid to the performance
gains and potential energy savings that can be achieved through these
extensions.
New Java
Extensions for ARM Cores
Andrew
Cummins - Java Program Manager, ARM Ltd.
ARM's new architecture
implements three ISAs. The core is synthesizable and can execute both
legacy and new software. This presentation is the first public disclosure
of this processor.
10:30 am: Morning Break
sponsored by
A
Hyper-Clocked picoTurbo™ pT-120™ CPU
Chip
Stearns - CEO, picoTurbo, Inc.
PicoTurbo has
developed a synthesizable processor core capable of executing the
ARM® (version 4T) instructions at clock rates nearing half a
GHz. This presentation is the first public disclosure of this core.
A High-Performance,
Easy-to-Use 64-Bit Embedded Core
Kevin
Daberkow - Manager, MIPS Core Development Team, LSI Logic
This presentation
discloses the EZ4021, a 64-bit 250-MHz embedded microprocessor. The
EZ4021 is an optimized implementation of a synthesizable core designed
for ease of use.
TX79:
A MIPS-Compatible Synthesizable Core with Extended Multimedia Instructions
Peter
Hsu -Chief Architect, Toshiba America Electronic Components, Inc.
This presentation
focuses on Toshiba's 128-bit TX79 core, which is a fully synthesizable
microprocessor core based on the MIPS RISC architecture. It utilizes
Toshiba's 0.18-micron process with 0.14-micron effective channel length
while running at over 200 MHz. Come learn more about Toshiba's answer
to the technical challenges of integrating a high-frequency processor
core within a conventional ASIC chip.
ST200:
A VLIW Architecture for Media-Oriented Applications
Fred
Homewood - VLIW Architecture Manager, STMicroelectronics, and Paolo
Faraboschi, Senior Research Scientist, HP Labs
The ST200-STB1
is the first implementation of the ST200 configurable VLIW core developed
jointly by HP Labs and STMicroelectronics. This presentation will
describe the interaction between the architecture, microarchitecture,
and compiler design for this processor.
dCF4/dt:
The First Derivatives of the v4 ColdFire Integrated Core
Joe
Circello - Chief Architect, Motorola SPS
As Motorola's
ColdFire has matured, this processor family has grown increasingly
to resemble the company's long-dominant 68K family in breadth and
scope. This newest iteration is no exception and will open new vistas
in performance (200+ MHz) and capability (enhanced MACs, support for
multiprocessing).
12:20 pm: Lunch
1:40 pm
Information Appliance Processors (Cores)
SH-5:
A First SuperH 64-Bit Core for SoC Design
Karl
Wang - Director of Advanced Microprocessor Core Development, Hitachi,
and Dominique
Henoff, ST50 Program Mgr. of Micro Core Dev. Div, STMicroelectronics
These companies
announced the SH-5 core at last year's Microprocessor Forum. This
time, they're ready to demonstrate how the core fits into a SoC design,
as well as give the first public disclosure of the core's multimedia
SIMD unit and the SuperHwy on-chip bus.
ARC
Tangent-A4: A Configurable Core with Enhanced DSP Features
James
Hakewill - Chief Architect, ARC Cores
First public
disclosure of ARC Cores' fourth iteration on a successful configurable
core with a faster pipeline, enhanced DSP, and new intrinsic in the
processor's function library.
Java
Execution in Native Mode Using Vulcan ASIC's Moon
Ben
Cheese - Joint Managing, Director, Vulcan ASIC Ltd.
This presentation
gives the first public details of the Moon Java Processor, introduced
in May. The processor is a 32-bit hardware implementation of Sun's
JVM, designed for embedded applications.
Q&A
Panel
3:30 pm: Afternoon Break
sponsored by 
3:50 pm: Panel:
Next-Generation Memory Technology
Peter
Glaskowsky - Senior Analyst and Senior Editor Microprocessor Report,
MicroDesign Resources
MDR analyst Peter
Glaskowsky hosts a roundtable discussion with executives and engineers
from major memory and core-logic vendors. The conversation will focus
on the memory requirements of PCs and servers over the next few years.
The needs for capacity, bandwidth, and low-latency access will be
described, and all of the major alternatives including Direct RDRAM,
DDR, and the Advanced DRAM Technology (ADT) effort will be explained
and compared.
4:40 pm: Panel:
The Future of the Microprocessor Industry: Technology, Business, and
Markets
Michael
Slater
Tom Riordan, QED;
Chris Rowen, Tensilica;
Glenn Henry, Centaur
Technology; Dave Epstein, Microprocessor Report Editorial Board; Dave
Ditzel, Transmeta
MDR founder,
Michael Slater will moderate a discussion among an exceptional group
of executives: microprocessor architects who now run companies. This
new class of leaders is unusually well equipped to provide insights
into the full spectrum of issues that will determine the future of
the microprocessor industry, from technology trends to business models
and market drivers. The panel will address questions such as:
- Are microprocessor
architectures stabilizing, or is the rate of change in fact increasing?
- How far will
the x86 architecture's grip on the industry extend?
- What applications
will drive future growth in the microprocessor industry?
- Are we reaching
a saturation of performance demand? If so, how will this change
the industry?
- What strategies
will enable small microprocessor companies to succeed in the face
of the industry behemoths?
- How will future
generations of process technology affect the microprocessor industry?
- Are single-chip
systems inevitable? Will discrete microprocessors survive?
5:30 pm: Microprocessor
Forum adjourns
Please Note:
All times are subject to change.
