Seminar
One: Monday October 4th
From SIMD through Reconfigurable Fabrics:
DSP Architectures in SoC Configurations
Presented by Max Baron
This architecture-oriented seminar will blend a guiding introduction
to digital-signal processor (DSP) functions and principles
of operation, with descriptions of different types of DSP
architecture and the applications and systems that will make
them shine.
The seminar will address the latest DSP-only engines and
the ongoing evolution of general-purpose processors' (GPP)
instruction-set architecture (ISA) toward efficient execution
of DSP workloads. The presentation will detail the latest
enhancements obtained by vendors evolving DSP products into
devices that can also undertake microcontroller tasks, including
execution of a SoC’s system software.
The interconnect architecture of DSP accelerators will
be discussed, categorizing these devices by how they relate
architecturally to the host processor, on-chip buses, and
memory hierarchy internal and external to the SoC.
Going beyond classical DSP configurations, the seminar
will cover arrays of processors, configurable and reconfigurable
architectures, and heterogeneous configurations, highlighting
for each its capability of functioning in a power-aware
environment or in specific handheld systems. The presentation
will include an extensive survey of chips and cores from
leading vendors. A comparison table will be provided at
the conclusion of the seminar.
Seminar Two:
Monday
October 4th
High-Performance Processors: Trends and
Implementations
Presented by Kevin Krewell
This seminar will explore the latest trends in high-performance microprocessors, including the move from advanced single-core microarchitectures to SoC and multicore designs. With chip designers placing an increasing number of relatively simple CPU cores on one die, and chips that can reconfigure their logic based on software demands, and CPU cores that can add new instructions to speed up specific algorithms, is general-purpose microarchitecture design passé? This seminar will examine the new ways in which today's designers are investing the larger transistor budgets provided by Moore's Law.
Some vendors are investing significant resources into new
architecture designs, while others are taking existing cores
and packing two or more on a die. A number of processors
have already incorporated multi-threading. Will multi-core
make multi-threading obsolete or is there an advantage of
having both technologies in one design? Some programs and
benchmarks will be amenable to the multi-core strategy,
but much legacy software performs best on high-performing
monolithic processors. In addition, on-chip bandwidth and
core-interconnects become as important as core performance
and cache size in system performance.
The seminar will examine present and future microprocessors
for the server, PC, notebook, and high performance embedded
markets and explore the design challenges each face. The
seminar will cover each major instruction set architecture
(ISA) including ARM, IA-64/EPIC, MIPS, Power, SPARC, x86
and, in addition, will also explore non-traditional and
user-configurable processor vendors. Design trade-offs involving
on-chip and external system buses will be covered as well.
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