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October
13th through 16th, 2003
Tuesday
Wednesday
Tuesday
Keynote:
Throughput
Computing
Greg Papadopoulos, Executive Vice President & CTO,
Sun Microsystems
Session
1: PC & Server Processors/Kevin Krewell, General
Manager, MDR
Introducing
the Transmeta TM8000 Efficeon Processor
David R. Ditzel, CoFounder and CTO, Transmeta Corporation
Two New VIA
Processors with Unique Features
Glenn Henry, President, Centaur Technology, VIA-Centaur
SPARC64 VI:
Fujitsu's Next Generation Processor
Takumi Maruyama, Manager, E Processor Development, Fujitsu
IBM POWER5
Processor
Dr. Balaram Sinharoy, POWER5 Chief Scientist, IBM Corporation
Sun Microsystems'
UltraSPARC IV Processors
Quinn A. Jacobson, Chief Architect of UltraSPARC IV
Series, Sun Microsystems
Session Q &
A Panel
Session
2: Extreme Processors/Tom Halfhill, Senior Analyst,
In-Stat/MDR
A New, High-performance,
Low-Power, Floating-Point Embedded Processor for Scientific
Computing and DSP Applications
Simon McIntosh-Smith, Director of Architecture, ClearSpeed
Technology Ltd.
Field-Programmable
Object Array (FPOA), a 1 GHz Processor for Signal and
Network Processing
Dirk Helgemo, Chief Architect, MathStar, Inc.
New StarCore
DSP Bridges the Gap Between General Purpose Computing
& Signal Processing
Dan Tamir, Core Architecture Manager, DSP Platforms, Motorola, Inc.
Superpipelined
Trimedia CPU
Jan-Willem Van de Waerdt, Chief Architect, Embedded
Processor Dept., Philips Semiconductors
A Massively
Parallel Processor Array for Communications
Peter Claydon, COO, Cofounder & Chief Architect,
picoChip Designs Ltd.
A Massively
Parallel Reconfigurable ULIW Core
Dr. Ir. Jeroen A.J. Leijten, Cofounder & Lead Architect,
Silicon Hive
Session Q &
A Panel
16th
Annual Microprocessor Report Awards
Nick Tredennick, Editor, Dynamic Silicon
Wednesday
Keynote:
The History and Future of Computer
Instruction Set Architectures
Fred Weber, CTO & Vice President, Computation Products
Group, Advanced Micro Devices
Session
3: High-performance Processors/Markus Levy, Senior Analyst,
In-Stat/MDR
High Performance
Processor for Deeply Embedded Applications
John Rayfield, VP of US Marketing, ARM
Practical Benefits
of Multi-Threaded RISC/DSP Processing
David W. Knox, Vice-President, Software, Imagination
Technologies
New 32-bit
Family from MIPS Technologies Offers the Fastest Synthesizable
Licensable Processor Core
Larry Hudepohl, Engineering Director, MIPS Technologies
Architectural
Extensions to the MIPS Architecture for High-Performance
Embedded Systems
Kevin D. Kissell, Architect, MIPS Technologies
Session Q &
A Panel
Session
4: Low-Power Processors/Max Baron, Principal Analyst,
In-Stat/MDR
ARC Unveils
Next-Generation ARCtangent A600 Processor
Dr. Nigel Topham, Chief Architect, ARC International
Mobile Applications
Processor with Enhanced Security
Simon Segars, Vice President, Engineering, ARM
SH-X: 4500MIPS/W
2-Way Superscalar CPU Core and its SoC Products
Shinichi Yoshioka, SH-X Project Manager, SoC Division,
Renesas Technology Corp.
Co-author Toshihiro Hattori, Director of Engineering
(Japan), SuperH, Inc.
Next-Generation
Processor Architecture for Innovative Convergence Platforms
John Vaglica, Manager, Advanced SoC Architecture Team,
Motorola, Inc.
Session Q &
A Panel
Special
Presentation - "TRIPS: Extending the Range of Programmable
Processors
Stephen W. Keckler, Assistant Professor, The University
of Texas at Austin
Panel:
"The End of Conventional Architectures"
Moderated by Peter N. Glaskowsky, Principal Analyst,
In-Stat/MDR
Doug Burger, Assistant Professor, University of Texas
at Austin
Bill Dally, Professor of EE & CS, Stanford University
Andy Glew, Senior Member, Technical Staff, AMD
Daniel Leibholz, Distinguished Engineer, Sun Microsystems
Robert Mykland, Founder & CTO, Ascenium Corporation
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2003
Proceedings
