Vol 16, Issue 17

April 29, 2002

Moving Targets

By Max Baron

For processor vendors, the embedded market represents a wealth of opportunity. Most "as soon as we get past the present economic situation" projections are optimistic, making this market a major source of revenue during the next few years. Embedded applications code reflects the physics of video, audio, communications media, and hard real-time control of mechanical devices. Beyond text and simple arithmetic, embedded applications require logic and mathematical operations for which some microprocessors and traditional memory hierarchies are less than efficient.

Established vendors of general-purpose processors (GPP)—whose processors' main value exists in the architecture's array of available software tools, operating systems, and applications—are looking for new ways to take these assets into the beckoning embedded market. The simplest approach toward achieving this end is to advocate the obvious: a GPP can do any task if it can deliver enough performance. This is a wonderful marketing message: it preserves the stability of the architecture and the value of the tools that support it, and it connects the system designer to the vendor's microarchitecture and semiconductor technology roadmaps.

The most obvious step toward differentiation is increased performance through higher frequency. But frequency is difficult to increase in standard products and hard cores, and it is even more difficult to guarantee in soft cores. Brewing for quite some time, an alternative solution to increasing performance is the use of multiple homogenous cores. Core vendors claim that it is easy to integrate several similar cores into a system-on-a-chip from the viewpoints of interface and validation. Multiple cores can offer "x times" the performance, at relatively low frequencies, if one knows how to extract that performance.

GPP core vendors point out that, as semiconductor technology moves below 100nm, multiple or complex cores will become less costly, and OEMs won't have to pay today's prices for the cores' silicon real estate. Power consumption has also been addressed: the power required by the processor(s) may be only a small part of total system power and becomes a "don't care." And let's not forget the flexibility that the programmability of a GPP core can deliver.

On the other hand, vendors of special-purpose processors are touting a different approach by fitting their processors' instructions and/or hardware to target applications. Their application-specific processors use memory organizations that are best configured for the tasks at hand and can deliver minimal access times for instruction and data fetches. Tailor-made designs consume less power and are less costly, since they don't have to carry the legacy instruction set architecture (ISA) of a general-purpose MPU. Cost is important in high-volume products: using submicron technology does not remove the problem of cost; it just rescales it.

The spectrum of special-purpose processors that are offered is as wide as the span of applications and as deep as the number of technologies that can be used. At the low end of the architecture spectrum, but the highest end of performance, are hard-wired state machines that offer little or no flexibility. The next step up is the FPGA/CPLD technology that mixes special cores with programmable logic and competes with less expensive, but riskier, ASIC technology aimed at high-volume applications. At the high end of the architecture spectrum, combinations of multiple special processors and arrays on a single chip can become too complex to program and require special intermediate-level instructions or functions delivered by their vendor. Advocates of special-purpose processors explain that simple application-specific designs can track semiconductor technology better than general-purpose processors and can take advantage of available parallelism and frequency earlier than GPPs. The development effort, and associated risk, that must be invested in a special-purpose design can present competitors with a higher barrier to entry than creation of a program that uses a GPP.

But behold! Architecturally, general-purpose and special-purpose processors are drifting closer to each other. Oftentimes, a special-purpose engine is designed to work with a general-purpose processor. To support this type of architecture, Xilinx will include four PowerPC processor cores in its largest Virtex-II Pro chip, which also features 206 multiply cores and more than 1,000 I/O pins. Altera uses a soft general-purpose processor, the Nios, and is expected to offer almost 100 complete DSP blocks integrated into its largest Stratix chip.

Following in the footsteps of desktop processors that have extended instruction sets to better cope with new applications, GPPs aspiring for leadership in the embedded markets have been extending their own instruction-set architectures. ARC allows designers to add custom instructions, while Tensilica's Xtensa users can add very large accelerator structures and generate software development tools that make new "native" instructions indistinguishable from the basic ISA. ARM prefers to introduce its own instruction extensions to help it use less memory and deliver increased performance for DSP, multimedia, and Java applications. ARM did make two exceptions by granting architectural licenses to Intel via Digital and to Motorola. MIPS Technologies (64 bits, multimedia, cryptography) and others have extended the MIPS instruction set.

The rapid morphing of special-purpose processors and extended-ISA processors has introduced hardware moving targets that increase the difficulty of creating efficient, stable software development tools. Special-purpose engines need software development tools to help their initial integration into a system and their subsequent reuse in other designs. For vendors of general-purpose processors, the time-tested strategy of providing software development tools and operating system ports may come into question as these are forced to track vendor ISA extensions and, in some cases, user-created extensions. Buffeted by special processors and DSP engines, each requiring its own development environment, even the best and highest-quality CPU software development tools begin to play a less pivotal role—similar to the role of the core they support—vis-à-vis the rest of the system. The overall experience of programming can be degraded by less user-friendly and lower-quality tools that may come with special-purpose intellectual property, be it acquired under license or created at home.

The wide spectrum of embedded processing and control justifies the coexistence and success of both general-purpose and special-purpose processors. A new breed of software must become available to support the complex and varied solutions that can be put together by hardware designers. The first rays of dawn came from ARC and Tensilica, which, at different levels, provided programming support for user-extended instructions. On April 16, Intel introduced its Integrated Performance Primitives (IPP) 2.0, claiming to provide more than 3,000 cross-platform abstractions of functions for signal and image processing applicable to Pentium 4, Xeon, Itanium, PXA250, and PXA210 and making them available through a single API that supports popular compilers under the Microsoft Windows and Linux operating systems.

ISVs: How about a common API for competing general-purpose and special-purpose processors, with code optimized for their specific ISAs?