In this era of specialized conferences for each vendor or
technology, In-Stat/MDR aspires to provide engineers and engineering
management with a single source to learn about the key technologies
that will determine the system architecture and form factor
even before a design begins. These technologies include the
processing element, core logic, operating system, design and
programming tools, and interconnect architecture, to name
but a few. The selection of each technology is driven not
only by the system's performance requirements and operating
environment, but also by the technology's maturity and by
industry support, availability, price, performance, and standards.
Given all these criteria, decisions are not easily made, but
they are critical to the performance, cost, and life-cycle
of the final product.
As part of our expanding scope, In-Stat/MDR is launching
a new forum to explore the key technology options for electronic
system design. The new forum, called Electronic Design Forum
(EDF), will be held October 7, 2004, following Fall Processor
Forum. Electronic Design Forum will focus on interconnect
options, including chip-, board-, and system-level interconnects.
The entire electronics industry is diligently working on
new high-speed interconnects to solve the performance bottlenecks
of older interconnect architectures. This effort, however,
is leading to multiple alternatives with no clear winner.
On one side, new chip interconnects will increase bandwidth
while drastically changing the architecture of single-board
computers and add-in cards. On the other side, new board and
system interconnects will lead to new system architectures
and network topologies. One new system architecture is AdvancedTCA
(ATCA), which is designed to meet the performance and flexibility
requirements of the telecommunications industry. ATCA consists
of a base specification, which defines the electrical and
mechanical standards, plus "dot" specifications, which define
the use of various high-speed protocols, such as Advanced
Switching, Fibre Channel, Gigabit Ethernet, InfiniBand, RapidFabric,
and StarFabric. Consequently, engineers face a growing number
of options, even within a single architecture.
The Electronic Design Forum will include representatives
from industry leaders—such as AMCC, Broadcom, Cadence,
Freescale, IDT, PLX, Vitesse, and Xilinx—and trade associations
discussing the use, application, and issues of these technologies
in an effort to sort through the confusion. The morning will
focus on the next generation of chip-level interconnects,
and the afternoon will focus on board- and system-level interconnects.
In addition, keynote presenter Tom Lagatta, group vice president
for enterprise computing at Broadcom, and a representative
from a major infrastructure provider (soon to be announced),
will discuss the changes in system design that result from
changes in technology and the outlook for the electronics
industry with new technology enablers.
The Electronic Design Forum will be held at the San Jose
Fairmont. More details on the event are available at www.mdronline.com/edf.
Please join In-Stat/MDR as we explore the technology options
for electronic system design.
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