Embedded Processor Watch

Editor: Jim Turley

In This Issue:

• Intel Prescribes Higher I2O Performance With i960RN
• Mitsubishi Enhances Strange M32R/D Processor
• Lexra's MIPS Clone Reaches Silicon; Evaluation Board Debuts
• Weird Product of the Week: I-Bus Guppy
• Industry Resources: Giving Up PCs for PLCs?
• New Embedded IC Announcements

Intel Prescribes Higher I2O Performance With i960RN

Intel has doubled the number of its I20-compatible microprocessors, from two to four, with the introduction of the i960RN and i960RM. The two chips, which are nearly identical, offer a big speed boost over the existing i960RP and 'RD chips, but won't be available until late this year. When the new i960RN and 'RM go on sale, they will likely be priced the same as the two current parts, pushing the 'RP and 'RD into low-end designs.

The 'RN offers several performance improvements over the 'RP, starting with a faster, 100-MHz i960 processor core. To support the higher speeds, the 'RN enlarges the caches to 16K and 4K (instruction and data). The chip's local memory bus has grown from 32 to 64 bits wide, with an extra 8 bits providing ECC (error-correcting code) security. The upstream and downstream PCI interfaces still run at 33 MHz, although the 'RN widens both to 64 bits each. (The 'RM is the same as the 'RN, but with 32-bit PCI interfaces.)

The i960RM and 'RN are the first to have an "application accelerator," an internal logic block that performs a logical exclusive-OR on data stored in local memory. Its purpose is to accelerate RAID striping, where data destined for the disks must first pass through a filter. Intel says the hardware assist cuts the time for this function by about two-thirds, versus the usual software-only approach.

Intel is the best-known proponent of the I2O (intelligent input/output) standard, a hardware and software architecture intended to offload a computer's disk and network tasks from the host processor onto an intelligent subsystem. I2O network cards and RAID controllers are becoming common in network servers and high-end workstations. Most of these subsystems use Intel's i960RP and 'RD chips, although PowerPC, MIPS, and x86 chips have been used as well. The major requirements for an I2O controller are two PCI interfaces and compatible message-passing hardware.

Intel has used the I2O standard to inject a little life into its foundering i960 family. Once the best-selling 32-bit RISCs in the world, the i960 architecture has fallen far, and fast, ranking well behind MIPS and SuperH, among others. I2O subsystems are, by definition, independent of CPU architecture; using intelligent I/O controllers, Intel has given a shot in the arm to its i960 family.

Mitsubishi Enhances Strange M32R/D Processor

Staying the course, Mitsubishi has enhanced and improved its peculiar microprocessor-cum-memory, the M32R/D. The newest version, dubbed M32Rx/D (note the "x"), enlarges the chip's DRAM capacity to 32 Mbits (4 Mbytes) and improves the chip's processor speed to 100 MHz. The part's external bus is now wider, at 32 bits, and faster, at 25 MHz. Pricing and availability have not been revealed.

Mitsubishi's M32 processors are, in a word, unique. Part microprocessor, part DRAM, they were among the first commercial devices to mix these two major features in a mass-produced part. The chip functions as both a processor and a synchronous DRAM (SDRAM). Its M32 CPU core is a 32-bit RISC processor that can execute code directly from the on-chip DRAM. A 128-bit bus between CPU and DRAM speeds cache line fills. An external bus allows off-chip access to memory and I/O. Conversely, the chip can act as a slave, serving as a 25-MHz SDRAM for other bus masters in the system.

The idea combining CPU and DRAM is not a new one; being able to mix these two opposite technologies in a commercially viable component is. The combined device promises many advantages for the embedded designer: lower power consumption, smaller PCB footprint, and reduced electromagnetic interference, to name a few. The part is not, however, without its faults. The current 66-MHz chips are not particularly fast by current standards; neither is the SDRAM's 25-MHz clock rate. Finally, Mitsubishi's proprietary M32 CPU architecture is virtually unknown and not well-supported with development tools. Mitsubishi's recent technology swap with Motorola, which gave it access to the 68K and ColdFire, may alter this situation within another year.

Lexra's MIPS Clone Reaches Silicon; Evaluation Board Debuts

Small startup Lexra Computing Engines (http://www.lexra.com) has received working silicon of its first microprocessor design, the LXR- 4080, and is offering the chip on an evaluation board for ASIC designers. The development board comes with a 100-MHz LXR-4080 processor, software tools, and PCI and serial connections to development systems.

Lexra's processor is interesting because it was developed without technical--or legal--help from MIPS Technologies. Lexra is not a licensed developer of MIPS processors, but the company was able to reverse-engineer the architecture and now sells the core as a high-level hardware description. The synthesizable nature of the LXR-4080 makes it different from other MIPS cores.

Predictably, the company has attracted the attention of MIPS Technologies' legal staff, which sued Lexra a few months ago. Interestingly, MIPS did not allege any patent infringement--only that Lexra was not entitled to use the word "MIPS" or part numbers beginning with the letter "R." Lexra has since altered its marketing literature.

Weird Product of the Week: I-Bus Guppy

Meeting a seemingly obscure need, I-Bus has produced a product it calls Guppy. Somewhat less fearsome than the company's Barracuda, Tigershark, and Thresher products, Guppy is a small printed-circuit board with three connectors that allows you to connect two different systems to the same floppy drive. I-Bus is available for questioning at 619.974.8400 or at http://www.ibus.com.

Industry Resources: Giving Up PCs for PLCs?

Then you might want to check out "Industrial Controls Intelligence & the PLC Insiders' Newsletter," a monthly subscriber-supported newsletter put out by Jack Grenard and Carefree Communications. For more information, call Carefree (Carefree, Ariz.) at 602.488.1462 or mailto:jgrenard@aol.com.

New Embedded IC Announcements

DiskOnChip 2200 (M-Systems) Nonvolatile memory device emulates a flash disk with TrueFFS drivers, with capacity from 2-72 Mbytes; fits in standard 32-pin JEDEC socket. Production: Now; Call M-Systems at 510.413.5950.

M48T559Y (STM) Popular Timekeeper nonvolatile SRAM with real-time clock is available in low-profile surface-mount package with detachable battery. Price: $7.43/1,000; Production: Now; Call STM at 781.861.2650.

CY7C42x1V, CY7C42x5V (Cypress) Line of synchronous, 3.3-V FIFOs has up to 1-Mbit capacity, 67-MHz clock rate, and dual-ported memory cells. Price: $5.15/10,000; Production: Now; Call Cypress at 408.943.2600.

HCS515 (Microchip) Code-hopping decoder for remote keyless entry systems handles reception and validation of code and learns new transmitters. Price: $1.77/10,000; Production: Now; Call Microchip at 602.786.7668.

SC112 (Semtech) Low-dropout regulator for small devices such as cellular telephones and bar code scanners; typical dropout of 180 mV at 50 mA. Price: $0.29/10,000; Production: Now; Call Semtech at 805.498.2111.