Embedded Processor Watch

Senior Editor: Tom Halfhill

Contributor to this issue: Keith Diefendorff, Senior Analyst

In This Issue:

• Motorola Thaws ColdFire V4
• Microware Ports OS-9 to MIPS
• Transmeta Lands Gateway-AOL Internet Appliance
• Coming Next Week: Embedded Processor Forum

Motorola Thaws ColdFire V4

By Tom R. Halfhill

It's coming a year later than Motorola had hoped, but the CF5407 -- the first standard chip based on the ColdFire V4 core -- is a significant improvement over the two-year-old CF5307. It delivers three times the raw performance, twice as many mips per megahertz, and nearly four times as many mips per watt. And the 5407 is almost pin compatible with the 5307, requiring only a lower Vcc supply (1.8V) and different clock inputs for its core, so developers can make boards that work with either chip.

Wisely, Motorola didn't tamper much with the basic design. The 5407 has the same integrated peripherals as its popular and proven predecessor. But by redesigning the execution pipeline, tripling the amount of cache, and enhancing some of the peripherals, Motorola was able to boost the performance and utility of an already versatile chip -- the 5307 won our Best Integrated Processor award for 1998.

The 5407 is sampling now and is scheduled for production in 3Q00. It's bargain-priced at $19.95, only $5 more than the current price for the much slower 5307. Embedded developers who remain devoted to the 68K architecture should bond quickly with the new chip, which is compatible enough with the 68K to make a transition to ColdFire relatively painless. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0515/142001.html).

Microware Ports OS-9 to MIPS

Microware has agreed to port its OS-9 embedded RTOS to the MIPS32 and MIPS64 architectures from MIPS Technologies. As part of the deal, Microware will also provide DAVID (digital audio/video interactive decoder), a software platform for digital-TV applications. DAVID uses Sun Microsystems' Java and supports digital broadcast standards in the U.S., Europe, and other parts of the world. For more information: http://www.mips.com and http://www.microware.com. --T.R.H.

Transmeta Lands Gateway-AOL Internet Appliance

Upholding Transmeta's promise that systems using its processors would be announced by midyear, Gateway has committed to using Crusoe processors (see Embedded Processor Watch #86, http://www.MDRonline.com/epw/issues/epw_86.html) in a new family of Internet appliances it is developing jointly with America Online. The Gateway-AOL appliances will also use Transmeta's Mobile Linux as the operating system and Netscape's smaller, faster "Gecko" Web browser.

This announcement, along with the strategic investment Gateway recently made in Transmeta, should be viewed as a significant vote of confidence in the startup company's code-morphing and power-saving technologies. The Gateway deal indicates Transmeta is having some success with its strategy of attacking the Internet-appliance market. If this early design win is an indication of things to come, it puts Transmeta on a path to being a real player in the market for x86-compatible processors. --K.D.

Coming Next Week: Embedded Processor Forum

More than 20 companies will reveal new microprocessors, processor cores, DSPs, and other technologies during the conference sessions at Embedded Processor Forum next week. Here's a summary:

MIPS64 20K (MIPS Technologies): the first public disclosure of the latest MIPS64-compatible processor core.

SB-1 (SiByte): the first public disclosure of SiByte's new superscalar MIPS64-compatible processor core.

PowerPC 750CX (IBM Microelectronics): the first public disclosure of the newest superscalar member of IBM's PowerPC 700 family.

DVine SM2700 (Silicon Magic): the formal introduction of the first standard product based on the DVine (DRAM vector engine) chip-multiprocessor architecture.

TriCore V1.3 (Infineon): the first public disclosure of a future TriCore chip that will implement the new version 1.3 architecture.

IMJAZZ-HW5-09 (Improv Systems): the formal introduction of a five-processor implementation of Improv's configurable data-path VLIW architecture.

A Low-Power MIPS32 Core (Alchemy Semiconductor): the first public disclosure of a new MIPS32-compatible core that runs faster than 500MHz and consumes as little as 200mW.

Crusoe (Transmeta): a closer look at the innovative LongRun power-management technology that allows Transmeta's x86-compatible Crusoe processors to dynamically scale their voltage and clock frequency to conserve power.

TMS320C55x (Texas Instruments): innovative approaches to power management that allow the latest 'C55x DSPs to consume only one-sixth as much power as current 'C54x DSPs while boosting performance.

aJ-100 (aJile Systems): the formal introduction of a bytecode-native Java processor that achieves real-time response.

Maverick 9213 (Cirrus Logic): previously unrevealed details about an ARM920T-based processor with integrated peripherals for digital-audio applications.

EEMBC Benchmarks (EDN Embedded Microprocessor Benchmark Consortium): the first public announcement of new benchmark tests on embedded processors.

CS2000 (Chameleon Systems): the first public disclosure of a network processor capable of executing 24 BOPS.

Manta (BOPS): new technical details about the first chip based on the ManArray DSP architecture.

NetVortex (Lexra): the first public disclosure of a new processor core with architectural enhancements for packet processing at OC-192 data rates.

Fast Pattern Processor (Agere): the first public disclosure of a processor that can recognize and classify millions of packets per second without the need for content-addressable memory or segmentation-and-reassembly (SAR) devices.

CPU Plug-Ins (ARC Cores): the first public disclosure of a configurable microprocessor core that works with third-party hardware and software enhancements.

T1025 (Tensilica): new extensions to the Tensilica Instruction Extension (TIE) language that allow developers to define new data types and create associated memory-access, arithmetic, field-manipulation, and Boolean instructions for Tensilica's configurable processor core.

High-Speed I/O (JAZiO): an explanation of new licensable I/O technology for embedded-system design.

PowerPC 440GP (IBM Microelectronics): the first public disclosure of a highly integrated embedded processor based on the PowerPC 440 core.

C6401 (Texas Instruments): technical details about the first DSP based on the TMS320C64x core, which boosts DSP performance by 10x.

Multicore Architecture for 3G Mobile (Motorola): the first in-depth look at Motorola's CPU/DSP architecture for third-generation wireless phones.

Carmel 2000 (Infineon): the first detailed disclosure of the second-generation Carmel DSP architecture.

There will also be six full-day seminars before and after the conference sessions:

"Information Appliances: Reshaping the Computer Landscape" presented by Michael Slater, founder and principal analyst at Cahners MicroDesign Resources.

"Digital Audio: Applications, Algorithms, and Implementation" presented by DSP analysts from Berkeley Design Technology Inc. (BDTI).

"Trends in Low-Power Embedded Processors" presented by Steve Leibson, chief embedded analyst at Cahners MicroDesign Resources.

"Communications Processors" presented by Bob Wheeler, principal consultant/analyst of Wheeler Consulting.

"Trends in High-Performance Embedded Processors" presented by Tom R. Halfhill, embedded analyst at Cahners MicroDesign Resources.

"Processors for Digital Signal Processing: Architectures and Trends" presented by Jeff Bier, cofounder and general manager of BDTI.

For more information about Embedded Processor Forum, visit the Cahners MicroDesign Resources web site at http://www.MDRonline.com/EPF. You may also call 800.527.0288 or 408.328.3900 for more information or to request a brochure.