Embedded Processor Watch

Senior Editor: Tom Halfhill

Contributor to this issue: Kevin Krewell, Senior Analyst

In This Issue:

• Intel Embeds Coppermine
• Agere's Pipelined Dream Chip
• TSMC Verifies 0.15µ MoSys Memory
• Cahners MicroDesign Resources Seeks New Analysts

Intel Embeds Coppermine

By Tom R. Halfhill

Intel has introduced five embedded processors based on the same 0.18-micron Coppermine die found in most Pentium III and Celeron processors for the desktop and mobile markets. Actually, the embedded versions of the chips are identical to the desktop/mobile processors, but Intel guarantees longer availability (at least five years) and is rounding up third-party support in the forms of operating systems and development tools.

Three of the new embedded processors are Pentium III designs, and two are Celeron designs. At the high end are a 733MHz Pentium III with a 133MHz system bus and a 700MHz Pentium III with a 100MHz system bus. Both have 256K of on-chip L2 cache. The third Pentium III processor runs at 500MHz with a 100MHz system bus.

At the low end (relatively speaking) are a 566MHz Celeron processor and a 400MHz Celeron. As with their desktop/mobile counterparts, these processors have only 128K of on-chip L2 cache. The 566MHz embedded Celeron has a 66MHz system bus, as do all desktop Celeron processors, but, like the 400MHz mobile Celeron, the 400MHz embedded Celeron has a 100MHz system bus. The different bus speeds and cache sizes are the results of Intel's market-positioning decisions, because all the chips use the same die. (The full version of this article is available to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0612/142403.html).

Agere's Pipelined Dream Chip

By Kevin Krewell

In January, Agere became the networking-processor business unit of Lucent Microelectronics, joining the ranks of a half-dozen other network-processor startups that have been absorbed into larger corporations.

Two-year-old Agere was founded to build a business around Vic Bennett's patent (U.S. 5,813,001) for "efficient search of a knowledge base to determine whether an object matches any plurality of knowledge base entries," which allows fast, efficient, and deterministic pattern searches. That search becomes a parallel tree search through the bit pattern to then determine a course of action -- in this case, making a routing decision on a data packet. The strength of the algorithm is that it can search the bit stream quickly and can pack the decision tree into a minimal amount of memory. Armed with this algorithm, Agere believes it can classify single-cell (ATM) packets up to and including layer 4 (the transport layer of the OSI model protocol stack) at 2.4Gb/s wire speeds (OC-48c, a SONET standard for optical-fiber backbones).

The Agere chip set consists of three chips: fast pattern processor (FPP), routing-switch processor (RSP), and Agere system interface (ASI). The first two chips perform wire-speed processing; the ASI and another microprocessor perform packet-speed (back-end) processing. The ASI provides a PCI interface to a microprocessor, such as PowerPC, to execute the routing protocol. The three chips in the Agere set use a total of only about four million transistors. Agere is promising a lot of magic from these modest chips, based mostly on its patented data-matching and pattern-matching logic, plus a collection of VLIW processors to power the routing engine.

The chip set requires two 64-bit-wide DRAM interfaces for packet data and seven 64-bit-wide synchronous SRAM interfaces for program and routing control. These nine 64-bit memory channels take up a large number of pins, which caused Agere to break the design into three chips rather than two or one. The three-chip set uses two 655-pin BGA packages (FPP and RSP) and one 448-pin BGA (ASI). The low integration of the chip set is a disadvantage, because the chip set, memory, and support logic take up roughly 20 square inches of board space, and twice that for a full-duplex OC-48c design. The chip set dissipates 10W at 133MHz in 0.18-micron CMOS.

Agere's Web site (http://www.agere.com/) contains a number of white papers and some product information. More detailed product information is available under NDA. (The full version of this article is available to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0612/142402.html).

TSMC Verifies 0.15µ MoSys Memory

Taiwan Semiconductor Manufacturing Co. (TSMC) has successfully produced MoSys 1T-SRAM in its new 0.15-micron logic process, only three months after producing MoSys test chips in its 0.18-micron process. This will allow TSMC's customers to use MoSys memory in cutting-edge system-on-a-chip designs. MoSys' 1T-SRAM technology essentially combines the advantages of DRAM and SRAM -- it uses only one transistor per cell but doesn't need to be refreshed and has low access latencies. For more information: http://www.tsmc.com and http://www.mosys.com. --T.R.H.

Cahners MicroDesign Resources Seeks New Analysts

Cahners MicroDesign Resources, the publisher of this newsletter as well as Microprocessor Watch and Microprocessor Report, and the organizer of Microprocessor Forum and Embedded Processor Forum, is seeking new analysts to join its team. Positions focused on either embedded processors or PC processors are available. Our analysts are highly visible thought leaders in the microprocessor industry and frequently meet with top architects and executives. Candidates must have at least five years of relevant design, marketing, or analysis experience as well as excellent communication skills. For more information, contact Keith Diefendorff (mailto:kdiefendorff@mdr.cahners.com).