Embedded Processor Watch

Senior Editor: Tom Halfhill

Contributors to this issue: Steve Leibson, Chief Embedded Analyst, Peter N. Glaskowsky, Senior Analyst

In This Issue:

• ARC Cores Encourages "Plug-Ins
• Vector DSP, FPU Extend Xtensa
• Chameleon Crosses CPU, FPGA

ARC Cores Encourages "Plug-Ins"

By Tom R. Halfhill

High-level synthesis tools and configurable CPU cores already bring some of the malleability of software to microprocessors. Now ARC Cores is taking the next step: CPU "plug-ins."

The technical concept and business model for ARC's plug-ins will be familiar to users of PC software. For programs such as Adobe PhotoShop, QuarkXPress, and Web browsers, plug-ins take the form of digital image filters, file-format converters, and multimedia players, and they are usually created by third-party developers. In a similar fashion, ARC is encouraging intellectual-property providers and even its own customers to develop and sell extensions to ARC's configurable embedded-processor cores. The plug-ins are aftermarket packages that add new features or application-specific enhancements to the cores -- just as plug-ins for popular PC programs add new features to the host applications.

Plug-ins could take the form of CPU-level extensions to the synthesizable cores (such as new instructions, registers, condition flags, and bus-interface gaskets) or low-level software (such as device drivers and protocol stacks). ARC expects that most plug-ins will be packages of hardware and software enhancements that adapt the CPU cores for various kinds of embedded applications, such as digital cameras or broadband modems.

Such plug-ins could save ARC's customers a significant amount of development time and money. It would be a much quicker path to market than developing all the intellectual property from scratch or buying it piecemeal from multiple suppliers. And it would also be an attractive solution for companies that lack the resources to tackle such an extensive development effort themselves. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0619/142503.html).

Vector DSP, FPU Extend Xtensa

By Steve Leibson

Tensilica's third version of its configurable processor core, called Xtensa III, adds a 32 x 32-bit multiplier, an IEEE-754 floating-point unit, and a vector DSP. The extra function units add considerable flexibility and processing horsepower to the existing core.

In particular, the vector DSP, dubbed Vectra, has its own large local memory and register set and compares favorably to what was TI's leading-edge standalone DSP (at least until the 'C64xx DSPs become available). The Xtensa FPU also has its own set of 16 floating-point registers and can sustain two floating-point operations per clock. Tensilica's software tools, including compilers, test suites, and synthesis scripts, are automatically tailored to the custom core configuration by the company's software generators.

The extra capabilities come at a price: a lot of extra silicon and additional power dissipation. The vector DSP and FPU each increase the basic core size by more than a factor of two, and power dissipation rises accordingly. Even so, the Xtensa core consumes no more than 4mm^2 (in a 0.18-micron process) and therefore constitutes only a small portion of any ASIC that incorporates it. The extra functional units added to Xtensa III definitely jump Tensilica's core out of the box of similarly performing 32-bit RISC processor cores. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0619/142502.html).

Chameleon Crosses CPU, FPGA

By Peter N. Glaskowsky

Chameleon Systems has introduced the CS2112 reconfigurable communications processor (RCP), the first chip in a family of RCPs Chameleon expects to introduce over the next year. As its name suggests, the RCP was designed for one specific class of applications: communications processing. Eventually, Chameleon's new architecture may be used in other ways, but the company has wisely decided to focus on one niche market before expanding into other areas.

The CS2112 includes a conventional 32-bit ARC RISC microprocessor core, a 64-bit memory controller, and a 32-bit PCI interface, but these are merely supporting actors. The real star of the show is a reconfigurable processing fabric (RPF) that consists of 12 "tiles." Each tile includes seven 32-bit integer datapath units (DPUs) and two integer multipliers, four 32-bit x 128-entry four-port static RAMs, and a control/logic unit (CLU) that manages data movement and processing.

Chameleon (http://www.chameleonsystems.com) has seen first silicon of the CS2112, which is 300mm^2 in a 0.25-micron, four-layer-metal process. Though this chip is priced at $295 in sample quantities, Chameleon expects to sell it for less than $100 in volume by the second half of next year. The next two members of this family, the CS2103 and CS2106, will have one and two slices (three and six tiles), respectively.

Along with silicon, Chameleon will deliver a software-development environment with a C compiler and a Verilog synthesizer, a chip-level simulator, a debugger, and a development board. The C language is used for the ARC core, while Verilog must be used for RPF configuration design.

Chameleon's focus on just one application, and its early work in adapting the CS2112 architecture to this application and in developing pieces of the needed software, make it more likely that Chameleon can turn its new architecture into a profitable business. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0612/142401.html).