Embedded Processor Watch

Senior Editor: Tom Halfhill

Contributors to this issue: Keith Diefendorff, Senior Analyst Jennifer Eyre and Jeff Bier, BDTI

In This Issue:

• MIPS 20Kc Is Fastest Licensable Core
• TI Releases Details About First 'C64x
• Cahners MicroDesign Resources Seeks New Analysts

MIPS 20Kc Is Fastest Licensable Core

By Keith Diefendorff

Like many microprocessor companies, MIPS Technologies sees digital-entertainment and networking as large and rapidly growing opportunities. Answering the call for the high-performance embedded processors these markets need, MIPS has designed a new microarchitecture, called the 20K, based on the MIPS64 architecture and enhanced with the MIPS-3D instructions for better geometry processing (see Embedded Processor Watch #63, http://www.MDRonline.com/epw/issues/epw_63.html). Speaking at last month's Embedded Processor Forum, Victor Peng, engineering director at MIPS, laid out the details of his company's newest and fastest 64-bit design.

The new design, code-named Ruby, will be sold commercially in two forms: a complete standalone microprocessor, called the R20K, and a licensable core, called the 20Kc, for use in ASICs, ASSPs, and SOCs. The new offerings extend MIPS's current family of licensable 32-bit low-end and 64-bit midrange devices, the 4Kc (see Embedded Processor Watch #51, http://www.MDRonline.com/epw/issues/epw_51.html) and 5Kc (see Embedded Processor Watch #72, http://www.MDRonline.com/epw/issues/epw_72.html). R20K silicon is expected this quarter, and the 20Kc core will see first silicon in 1Q01.

As typical embedded processors go today, the 20K is quite aggressive, and it will probably fulfill MIPS's claim of being the highest-performance licensable core. The 20K will operate at up to 600MHz in a 0.18-micron six-layer-metal process (at nominal channel lengths), delivering an integer performance of around 1,200 Dhrystone 2.1 mips and a floating-point 3D-geometry performance of 2.4 GFLOPS and 30 million polygons per second. Yet at only 34mm^2, including dual 32K caches, the core is small enough to be a candidate for even low-cost embedded systems.

MIPS's play for the IP (intellectual-property) business has already cleared a big hurdle. Back in the first quarter of this year, TSMC announced it had licensed the 20Kc core from MIPS. TSMC, which is the largest semiconductor foundry in the world by a wide margin (see Embedded Processor Watch #103, http://www.MDRonline.com/epw/issues/epw_103.html), is a primary source of IP modules to the worldwide design community. With the 20Kc available through this source, startup and entrenched companies alike will have easy access to it. And as the highest-performance core in TSMC's IP portfolio, the 20Kc will be the obvious choice for a number of those companies.

Both the digital-entertainment and the network-processing markets are large and growing rapidly. These markets encompass a wide and diverse set of needs and customers. Some designs will need the absolutely highest performance, and for those, a special-purpose network processor or a high-performance SiByte solution may be best. For a large number of designs, however, the ability to easily license an off-the-shelf core that has good performance will be a better solution. For those designs, the 20Kc looks like a great product. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0703/142701.html).

TI Releases Details About First 'C64x

By Jennifer Eyre and Jeff Bier Berkeley Design Technology Inc. (BDTI)

At Embedded Processor Forum 2000, Texas Instruments revealed new details about the first implementation of its recently announced high-performance DSP architecture, the TMS320C64x. The TMS320C64x is the successor to TI's well-known TMS320C62x architecture and bumps up the earlier processor's performance with significant architectural enhancements and a much higher clock speed (see Embedded Processor Watch #90, http://www.MDRonline.com/epw/issues/epw_90.html). Without going so far as to announce a specific chip, TI lifted the veil just enough to disclose new information about the memory structure and peripherals that will be included in the first 'C64x product.

The 'C64x chip will contain two level-one (L1) caches, one for data and one for instructions. Each of the L1 caches contains 16K of memory (four times that of the L1 caches on the 'C6211). The L1 caches are fed by a unified level-two (L2) cache, which contains four 32K memory banks totaling 128K (double the L2 of the 'C6211). The L2 cache can be configured as noncached RAM, as a set-associative cache, or as a partitioned combination of the two. The L2 cache is fed via what TI calls an enhanced DMA controller, or EDMA. The EDMA supports 32 channels, and TI claims it can support more than 2.6GB/s of bandwidth. The chip also will include three multi-channel buffered serial ports, three timers, and three off-chip interfaces: a 64-bit interface for connection to memory, a 16-bit interface for I/O, and a 32-bit host-port interface.

When Texas Instruments introduced the 'C62x several years ago, the processor drew widespread attention because of its huge speed advantage, but its success in the market has been somewhat hampered by its high energy consumption and poor code density. With the 'C64x, TI has taken steps to address these issues, but in the process it has created some new trade-offs -- particularly in the use of cache memory. The problem of execution-time predictability is mitigated somewhat, because L2 cache can be configured as RAM, but most other (noncached) DSP processors don't have this problem at all. Then again, most other DSP processors won't be running at 1.1GHz.

It remains to be seen whether TI's newest fire-breather will find acceptance in the broad market or will mainly serve to give TI performance bragging rights while it goes about selling millions of its low-power 'C5x chips. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0626/142606.html).

Cahners MicroDesign Resources Seeks New Analysts

Cahners MicroDesign Resources, the publisher of this newsletter as well as Microprocessor Watch and Microprocessor Report, and the organizer of Microprocessor Forum and Embedded Processor Forum, is seeking new analysts to join its team. Positions focused on either embedded processors or PC/server processors are available. Our analysts are highly visible thought leaders in the microprocessor industry and frequently meet with top architects and executives. Candidates must have at least five years of relevant design, marketing, or analysis experience as well as excellent communication skills. For more information, contact Steve Leibson (mailto:sleibson@mdr.cahners.com).