Embedded Processor Watch

Senior Editor: Tom Halfhill

Contributors to this issue: Keith Diefendorff, Jennifer Eyre and Jeff Bier, Berkeley Design Technology, Inc.

In This Issue:

• IBM Brings L2 Onto PowerPC 750
• Motorola Pairs StarCore with MCore for 3G SOC

IBM Brings L2 Onto PowerPC 750

By Keith Diefendorff

At the recent Embedded Processor Forum, PowerPC architect Peter Sandon described IBM's newest PowerPC processor, the 750CX. The CX uses the same basic core as the 750 (G3) IBM currently sells to Apple for use in iMacs and PowerBooks, but the new chip includes a number of cost and performance enhancements. The most notable improvement is the addition of an on-chip L2 cache, a feature made possible by the use of IBM's 0.18-micron six-layer-copper CMOS-8S process.

The new on-chip L2 cache is 256K in size and is two-way set-associative. An L2 hit imposes an L1 miss penalty of five cycles, compared with eight cycles for the external L2 on the 750. The CX can transfer an entire 32-byte line into the L1 in four cycles, whereas the 750 requires eight cycles (with half-speed cache bus and commodity SRAMs). IBM estimates that at 550MHz, the CX will achieve a SPECint95 (base) score of 22.4 and a SPECfp95 (base) score of 13.3. This SPECint score indicates that the 750CX has about 5% better performance than a 750 with a 256K external L2 at the same clock rate, or about the same performance as a 750 with a 1M external L2 and a 10% lower frequency. Thus, since the CX operates at a 10% higher frequency than the 750, the CX essentially eliminates the cost of 1M of SRAM cache without sacrificing any performance.

In addition to eliminating the cost of 1M of SRAM, the 750CX die will also cost less to manufacture than the 750. The 750CX has a die size of only 42.7mm^2, almost the same size as its 40mm^2 predecessor. Even though the 0.18-micron CMOS-8S process used for the CX is currently a somewhat more expensive process than the more mature 0.22-micron copper CMOS-7S process used on the 750, the 750CX design eliminates the precision resistors required in the 750 design, thereby substantially lowering process costs.

The most significant reduction in manufacturing cost, however, comes from the use of a new low-cost organic-laminate BGA package. With this package, IBM breaks with its traditional C4-bonding technique (flip-chip), opting instead for old-fashioned wire-bond technology. This choice seems like a giant step backward for IBM, because C4 -- a technology IBM pioneered -- offers dramatically superior electrical characteristics.

At the least, the 750CX will provide a cost-effective upgrade for current PowerPC 750 customers. Apple, for one, should find the new part attractive for its low-end and portable boxes, although it needs to get on with its conversion to G4 processors and may not wish to get sidetracked with a short-term solution. The CX will provide, however, a very attractive upgrade for current 750 embedded customers. And in the embedded market, the new chip is sufficiently compelling that it may even attract new customers into the PowerPC camp. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0724/143001.html).

Motorola Pairs StarCore with MCore for 3G SOC

By Jennifer Eyre and Jeff Bier, Berkeley Design Technology, Inc.

At the recent Embedded Processor Forum, Motorola announced a new SOC architecture for implementing third-generation (3G) wireless terminal devices: the company will team a StarCore SC140 DSP core with Motorola's MCore architecture on a single chip. Motorola did not announce a specific product, instead stating that it will customize the mixture of peripherals, memory, and I/O to match the needs of specific applications. The mixture may include customer-supplied IP as well as Motorola-designed IP blocks.

At the Forum, Motorola acknowledged that the two cores alone are not sufficient for a complete 3G solution, and that SOC designers will have to add hardware coprocessors and accelerators to provide the needed additional performance. No other processor vendor has announced any processor (or two-processor combination, for that matter) capable of handling the demands of a full-blown 3G wireless appliance without additional hardware, so Motorola is not alone in this performance gap. Motorola expects to fabricate devices using 0.18-micron technology, with a migration path to 0.13 micron.

The particular variant of the MCore architecture that will be included in the SOC is the M340, which provides its own instruction/data cache and MMU. The M340 will execute at 100MHz. The SC140 DSP core will execute at 200MHz (significantly slower than the SC140's current top speed of 300MHz). Running interference between the two cores is an "Inter-Processor Communication Module" (IPCM), which is responsible for intercore data transfers and transfers between the cores and external memory. Motorola claims that the IPCM, which includes 32 channels of DMA and will execute at 100MHz, will alleviate data bandwidth bottlenecks and enable efficient memory sharing between the cores.

This is the second device Motorola has announced that includes an SC140; the MSC8101, announced in September 1999, includes a 300MHz SC140 and targets demanding line-powered applications such as cellular base stations. StarCore (the joint DSP development center of Lucent and Motorola) has claimed that the SC140 architecture is unusual in that it not only provides industry-leading performance but is the first high-performance DSP that is sufficiently energy-efficient to enable its use in portable devices. With Motorola's recent announcement, it appears that the company intends to fully capitalize on the core's unusual combination of strengths. This is probably the first time a single DSP core has targeted both the infrastructure equipment side and the portable side of a wireless application; using the same core for both may provide significant benefits in terms of code and knowledge-base reuse.

With this announcement, Motorola is challenging both ARM and Texas Instruments; ARM has the dominant MCU architecture in portable wireless devices, and TI claims that roughly 70% of wireless handsets contain TI DSPs (often on the same chip as an ARM). Obviously, Motorola is hoping to snag some of these two companies' market shares with its MCore/SC140 combination.

Motorola has an unusual position in this market, in that it provides both processors for cell phones and the cell phones themselves. This situation may be an advantage, in the sense that Motorola may be inclined to use its own chips in its cell phones. It may also be a disadvantage, however, since, in some cases, Motorola will be competing with its own semiconductor customers. (The full version of this article is available online to Microprocessor Report subscribers at http://www.MDRonline.com/mpr/h/2000/0724/143004.html).