Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Tom Halfhill and Peter N. Glaskowsky

In This Issue:

• PowerPC 440GP: Great Communicator
• BOPS Debuts Manta Silicon
• Embedded Java Chips Get Real

PowerPC 440GP: Great Communicator

By Tom Halfhill {7/31/00-01}

Merge a Corvette and a Cadillac and youíll get a Detroit disaster. Yet IBM has successfully created a similar hybrid by crossing a fast PowerPC 440 core with the luxury features of a highly integrated communications chip. The result is the PowerPC 440GP, which IBM disclosed last month at Embedded Processor Forum.

The 440GP is the first chip to use the PowerPC 440 embedded-processor core, which IBM previously unveiled at last fallís Microprocessor Forum (see Embedded Processor Watch #71, http://www.MDRonline.com/epw/issues/epw_71.html). The 440GP is also the first implementation of Book E, the embedded PowerPC architecture defined by IBM and Motorola (see Embedded Processor Watch #50, http://www.MDRonline.com/epw/issues/epw_50.html). In another first, it has a 128-bit version of IBMís on-chip CoreConnect bus (see Embedded Processor Watch #57, http://www.MDRonline.com/epw/issues/epw_57.html). Reaching clock speeds of 400-500MHz, the 32-bit 440GP is also one of the fastest embedded processors on the market.

But performance is only half the story. The 440GP comes loaded with on-chip peripherals and interfaces: dual Ethernet media-access controllers (MACs), a double-data-rate (DDR) SDRAM controller, a PCI/PCI-X controller, 64K of cache, and 8K of 128-bit SRAM, plus a liberal assortment of UARTs, I2C interfaces, general-purpose I/O ports, and timers. IBM designed the 440GP for network-oriented embedded applications that need high performance, such as cellular base stations, storage-area networks, RAID controllers, and network printers.

IBM appears to be building a family of network-oriented embedded processors that someday could be as broad as Motorolaís PowerQUICC line. The 440GP and 405GP are early members of that family. Future members will reach for higher clock speeds and likely integrate even more features. It will be interesting to see how Motorolaís first implementation of Book E stacks up against IBMís -- and how well the two companies can manage their odd-couple relationship as simultaneous PowerPC partners and rivals. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2000/0731/143101.html).

BOPS Debuts Manta Silicon

By Peter N. Glaskowsky {8/7/00-03}

Some two and a half years after first describing its ManArray processor architecture at the Microprocessor Forum, BOPS has shown the first ManArray-based chip. In his presentation at the Embedded Processor Forum in June, David Baker, vice president of BOPS, described Manta, a chip with four DSP processing elements (PEs), each capable of 40 operations per clock at 125MHz.

BOPS will use the 412-pin, 4W Manta as a proof-of-concept vehicle for the ManArray architecture. The company stresses that Manta was designed using a standard ASIC design flow and is built in TSMCís mature 0.25-micron, five-layer-metal process. Although the chip is a good prototyping vehicle, BOPS expects customers to build application-specific chips in faster processes to achieve substantially higher performance.

The first Manta chip is available in a PCI-bus evaluation board known as Jordan, which also includes a QED RM5231 MIPS-compatible processor and 64M of SDRAM. Although Manta is not available separately, the Jordan board is priced at $9,995 bundled with the BOPS software development kit. For more information, visit BOPS online at http://www.bops.com. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2000/0807/143203.html)

Embedded Java Chips Get Real

By Tom R. Halfhill {8/7/00-02}

Java and real-time processing usually go together like coffee and ketchup. But a Silicon Valley startup, aJile Systems, has a new Java chip that handles interrupts in real time and doesn't need a third-party RTOS. It also allows embedded-system developers to write all their software in Java -- even device drivers and other low-level code that normally would be written in C or assembly language.

AJile's aJ-100 microprocessor is based on the 32-bit JEM2 Java chip developed by Rockwell-Collins. JEM2 is an enhanced version of JEM1, created in 1997 by the Rockwell-Collins Advanced Architecture Microprocessor group. Rockwell-Collins originally developed JEM for avionics applications by adapting an existing design for a stack-based embedded processor.

Although Rockwell-Collins is using JEM2 for internal research and development, the company decided not to sell the chip on the merchant market. Instead, it exclusively licensed the design to aJile, which was founded last year by engineers from Rockwell-Collins, Centaur Technologies, Sun Microsystems, and IDT. AJile has wrapped additional on-chip memory and peripherals around the JEM2 core to create a more-integrated chip that has low power consumption (about 1mW per MHz) and fast interrupt handling (500ns at 100MHz).

AJile's goal is to penetrate embedded markets that until now have been off limits to Java because of high cost, low performance, and excessive power requirements. By programming in Java, developers can write more-portable code while leveraging Java's productivity advantages over C/C++ and assembly language.

Development boards based on a JEM2 chip with an FPGA are available now, and samples of the aJ-100 are scheduled to be available this fall. Production is expected to begin by the end of the year. Fabricated in a 0.25-micron CMOS process, the fully static core runs at 100MHz at 2.5V (with 5V-tolerant I/O) and occupies less than 1mm^2 of die area. With integrated peripherals and 48K of on-chip SRAM, the total die area is less than 16mm^2. The chip is packaged in a 176-pin LQFP and will cost $15 in 10,000-unit quantities. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2000/0807/143202.html).