Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Steve Leibson, Cary Snyder and Mark Long

In This Issue:

• XScale (StrongARM-2)
• Embedded Tidbits
• Info on the Microprocessor Forum 2000 October 9-13, 2000

XScale (StrongARM-2) Muscles In 1,000 mips at 900mW to 62 mips at 10mW, Sleeps at 0.1mW
By Steve Leibson {Posted 9/11/00-01}

The latest incarnation of StrongARM, now renamed XScale, is an embedded processor microarchitecture that pushes both the lowest power dissipation (10mW) and highest performance (1,000 Dhrystone 2.1 mips) envelopes of the embedded world. Naturally, you don't get both low power dissipation and extremely high performance at one time. You do get your choice. The low-power characteristics derive from design techniques that are becoming standard in processor design: extensive use of clock gating, circuit tricks, and dynamic voltage and frequency scaling. Improved processing performance stems from a high maximum clock rate (800MHz); an enhanced ARM V5TE instruction set; larger caches; a branch-target buffer that provides dynamic branch prediction; and additional SIMD instruction enhancements.

XScale's designers have added a 40-bit accumulator, which lives in the ARM coprocessor space, and six new SIMD coprocessor instructions that use this accumulator. Intel says it plans to use these SIMD extensions for audio processing and has defined a coprocessing engine with eight accumulators, although implementing just one in this incarnation. Intel has added these instructions through ARM's coprocessor mechanism, but actual implementation is part of the processor core. Intel has thus employed the standard calling mechanism that ARM created to allow licensees to add architectural improvements, while implementing the enhancements in a way that achieves single-cycle performance and also highlights the special nature of Intel's ARM license. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mpronline.com/mpr/h/2000/0911/143701.html).

Embedded Tidbits
by Mark Long

Atmel Ships RISC-Based Programmable SOC Atmel Corporation has begun shipping its RISC-based FPSLIC (Field Programmable System Level Integrated Circuit), which consists of embedded system blocks that include a processor, peripherals, memory, programmable logic, and other IP cores. The system on a chip (SOC) combines an embedded AT40K FPGA core with an AVR 8-bit RISC microcontroller (see MPR 7/14/97-02, "Atmel AVR Brings RISC to 8-Bit World"), two UARTs, timer/counters, interrupt controller, programmable I/O ports, and 36KB of SRAM. Additional peripherals and custom logic can be programmed in the FPGA. The FPSLIC family targets systems requiring an 8-bit microcontroller and up to 50,000 gates of programmable logic (FPGA or PLD). Atmel claims that the SOC, with 30 mips at 40MHz, consumes only a fraction of the power of conventional FPGA devices. The 1.3-million-gate-equivalent AT94K40 FPSLIC device is sampling now and is priced from $50. Additional AT94K family members will start shipping during 4Q00. Prices in 2001 for AT94K products will start below $7 in production volumes of 250,000 units. The SystemDesigner EDA tool suite for FPSLIC, which is available now for use on Windows 95/98/200/NT platforms, is priced at an annual subscription rate of $995. For more information: www.atmel.com.

Triscend Rolls Out 32-Bit Configurable SOC

Triscend Corporation has introduced a family of 32-bit configurable system-on-chip (CSOC) devices, each of which contains a microprocessor, embedded programmable logic, memory, and a dedicated system bus. The A7 family consists of four devices, all of which incorporate the ARM7TDMI processor core. The A7 CSOC family is fabricated at Sharp Electronics in Japan on a 0.25-micron CMOS process. The devices have a 2.5V core with 3.3- or 2.5V I/Os. Directly accessible from the A7 chip itself are timers, serial ports, and other peripheral devices, as well as system features like a memory-interface unit, a clock, reset and power-management circuits. The A7 family features cache memory, a four-channel DMA controller, an external memory interface unit, and advanced system-debug capabilities integrated with Triscend's Configurable System Interconnect (CSI) bus and Configurable System Logic (CSL). The CSI bus consists of a 32-bit address bus and a 32-bit data bus running at transfer rates of 265MB/s. Triscend's CSL uses SRAM-based cells to implement the functions defined by the soft IP peripherals and custom logic. The logic matrix is integrated with the system and the CSI bus to enable a "drag and drop" configuration of the CSOC. The logic matrix also supports advanced real-time processor-synchronized debugging of the entire system. Pricing for the A7 family starts at $12.95 in quantities of 10,000. Available now, the TA7S20, which contains 2,048 CSL cells, comes in 128LQFP, 208QFP, 280BGA, and 484BGA packages. Available 1Q01, the TA7S05 contains 512 CSL cells and will be available in 128LQFP, 208QFP, and 280BGA packages. Available during 3Q01, the TA7S12 will feature 1,152 CSL cells and 128LQFP, 208QFP, and 280BGA packaging. Slated for introduction in 2Q01, the TA7S32 will feature 3,200 CSL cells and 208QFP, 280BGA, and 484BGA packaging. For more information: www.triscend.com.

LinkUp Development Board to Support PalmPalm's 32-Bit OS

Seoul-based PalmPalm Technology and LinkUp Systems Corporation have announced that the LinkUp L7200 system-development board now supports Tynus, PalmPalm's Linux-based operating system. The 32-bit OS, which features a kernel that runs in less than 500K of RAM, provides APM and ACPI-like power management for battery-operated devices. LinkUp Systems supplies the L7200 processor-plus-peripherals family for creation of Internet appliances (see MPR 8/21/00-01, "LinkUp Systems Brushes Bluetooth"). The single-chip devices in the L7200 family include an ARM720T processor core, an integrated DSP, and peripherals such as LCD controllers, SDRAM controllers, a flash memory, smart card and Multimedia card interfaces, a DMA controller, and serial interfaces. The LinkUp development system consists of the L7200SDB development board and associated software that offers support for low-level driver APIs (L7200API) in source form. A complete software toolkit (L7200TLK), which is optimized for the on-chip DSP coprocessor of the L7200 device, is also available. The debug environment consists of an ARM debug monitor and Multi-ICE in-circuit emulator through JTAG interface. For more information: www.palmpalm.com.

Scenix Announces Ethernet Evaluation Kit

Scenix has introduced an Ethernet Evaluation Kit that will permit designers to develop and evaluate embedded products featuring both Internet and Ethernet connectivity. The Ethernet Evaluation Kit is also intended to provide designers with hands-on experience with the SX-Stack, a configurable combination of standard Internet protocols implemented as Virtual Peripheral modules. The following modules constitute the SX-Stack: Point-to-Point Protocol (PPP); Internet Protocol (IP) and Internet Control Message Protocol (ICMP); User Datagram Protocol (UDP) and Transmission Control Protocol (TCP); Simple Mail Transfer Protocol (SMTP), Hypertext Transfer Protocol (HTTP), and Post Office Protocol (POP3). Two configurations are offered. The iSX Web Server, which consists of the PPP, TCP/IP, and HTTP Virtual Peripheral modules, allows a standard browser to access and view stored Web pages. The eSX E-Mail Appliance, which consists of the PPP, TCP/IP, SMTP, and POP3 modules, allows both transmission and reception of email messages. The demonstration board includes a 50-mips SX52BD Embedded Internet Processor and an external 10Base-T Ethernet interface chip. The iSX Web Server and eSX E-Mail Appliance are loaded into the processor's flash/EEPROM memory. The kit contains a demonstration board, an AC power supply, a 9-pin-to-9-pin serial cable, a user's guide, and a CD-ROM containing the source code for the protocol modules. Available now, the Ethernet Evaluation Kit is priced at $99.00. For more information: www.scenix.com.

Altera Launches SOPC Design Courses

Altera Corporation has announced the availability of online training classes for its system-on-a- programmable-chip (SOPC) designs. Developed in partnership with Ictips.com, the Internet-based courses have been designed to train engineers on advanced programmable logic device (PLD) technology. Three courses are currently available. "Project Management & Compilation Using Quartus Software" provides an overview of the Quartus design environment. "Examining & Improving Timing Results in the Quartus Software" describes the way to view Quartus timing results after compilation and the way to use timing settings to improve those results. "APEX 20K Device Architecture Basics" provides an overview of the APEX 20K and APEX 20KE device architectures. Forthcoming courses are expected to focus on the Excalibur embedded processor as well as on other devices and software products that Altera intends to introduce in the near future. According to Altera, the courses feature an interactive environment including pop quizzes, graphics, animation, and sound to fully illustrate concepts. Each course will take approximately three to four hours to complete and can be reviewed at any time for one month after purchase. Each of Altera's online training courses is currently available in exchange for a $95 registration fee at www.altera.com.

Microprocessor Forum 2000 October 9-13, 2000 San Jose Fairmont Hotel

"The microprocessor industryís most important week of the year"

Microprocessor Forum 2000 Program Highlights:

Get breaking details on new chips and architectures from AMD, ARC Cores, ARM Ltd., Centaur Technology, Hewlett-Packard, Hitachi, IBM, Improv Systems, Intel, LSI Logic, Micron Technology, Motorola, picoTurbo, Samsung, SiByte, STMicroelectronics, Toshiba, Vulcan ASIC Ltd., Xstream Logic, and ZF Linux Devices

Conference Day One - October 10

++ Keynote ++

Dr. Robert Morris - Director, Almaden Research Center, Vice President for Personal Systems and Storage, IBM Corporation

Pervasive Computing: Technology, Crossings, Issues, and Implications

The time is approaching when we'll be freed from the confines of a fixed computing environment and computing will become pervasiveóaround us in our car, home, and office. In this presentation, Dr. Morris will explore the technology thresholds in miniaturization, usability, and portability that are making pervasive computing possible, while addressing the bandwidth, security, and social issues that will have to be overcome before pervasive computing becomes a reality.

Sessions with heavy embedded processor content include:

Conference Session 3 ++ Network Processors ++

Moderator - Linley Gwennap, founder of The Linley Group

- An Application Specific Extension to the MIPS Architecture for Network Processing * Michael Uhler - Director of Architecture, MIPS Technologies

- SB-1250: A High Performance, Power Efficient Chip Multiprocessor (CMP) Targeting Networking Applications * Jim Keller - Corporate Fellow and Chief Architect, SiByte, Inc.

- XStream Logic's Optical Network Processor * Mario Nemirovsky - Founder, CTO, and Chief Architect, XStream Logic Inc.

- Acappella: A Platform for Multi-Channel Voice Processing * Lloyd Palum - Principle Staff Engineer, Improv Systems Inc.

- New Developments in Intel's Internet Exchange Processor Family * Matthew Adiletta - Intel Fellow and Director, Communication Processor Architecture, Intel Corp.

Conference Session 4 ++ Information Appliance Processors ++

- ARM Media Extensions * John Rayfield - Director of Technical Marketing, ARM Ltd.

- New Java Extensions for ARM Cores * Andrew Cummins - Java Program Manager, ARM Ltd.

- A Hyper-Clocked picoTurboô pT-120ô CPU * Hong-Yi Chen - CTO, picoTurbo, Inc.

- A High-Performance, Easy-to-Use 64-Bit Embedded Core * Kevin Daberkow - Manager, MIPS Core Development Team, LSI Logic

- TX79: A MIPS-Compatible Synthesizable Core with Extended Multimedia Instructions * Peter Hsu -Chief Architect, Toshiba America Electronic Components, Inc.

- ST200: A VLIW Architecture for Media-Oriented Applications * Fred Homewood - VLIW Architecture Manager, STMicroelectronics, and Paolo Faraboschi-Senior Research Scientist, HP Labs

- dCF4/dt: The First Derivatives of the v4 ColdFire Integrated Core * Joe Circello - Chief Architect, Motorola SPS

- SH-5: A First SuperH 64-Bit Core for SoC Design * Karl Wang - Director of Advanced Microprocessor Core Development, Hitachi, and Dominique Henoff, ST50 Program Mgr. of Micro Core Dev. Div, STMicroelectronics

- ARC Tangent-A4: A Configurable Core with Enhanced DSP Features * James Hakewell - Chief Architect, ARC Cores

- Java Execution in Native Mode Using Vulcan ASIC's Moon * Ben Cheese - Joint Managing, Director, Vulcan ASIC Ltdv

+ Six full-day seminars on todayís hottest microprocessor applications: * information appliances * networks * high-performance embedded * multimedia * DSP and digital audio

Now is the time to register -- For more information please visit our web site at http://www.mdronline.com/mpf Or call 1.800.527.0288