Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Michael Slater, Markus Levy and Mark Long

In This Issue:

• Rethinking Web Appliances
• EEMBC Observations: Part II, Analysis and Mysteries
• Embedded Tidbits
• Lots of Action at Embedded Systems Conference West

Editorial: Rethinking Web Appliances

By Michael Slater {9/25/00-01}

As long-time readers of my columns are well aware, I have been enthusiastic about the prospects for Web appliances, Web tablets in particular, to free the Internet from the confines of the PC. As I have watched numerous companies attempt to launch such products during the past year, however, the depth of the challenge has become more apparent. To think clearly about Web appliances, it is first essential to be clear about the market segment being targeted. The popular argument for Web appliances is that they will enable non-PC users, people who haven't bought a PC, for reasons of cost or complexity to get on the Web. If the Web is to become truly ubiquitous, which is inevitable, it needs access devices that are cheap, unintimidating, and easy to use. More than half of U.S. homes have PCs, but that still leaves nearly half of them without access to the Web, and penetration is much lower in the rest of the world.

The problem with Web appliances as products for the "other half" is that new types of devices are most readily sold to early adopters, a category that clearly excludes people who don't yet have a PC. Selling new types of consumer devices to people who are inherently slow to adopt new technology is a daunting proposition. This is a key reason that WebTV, after years of effort and Microsoft's backing, has stagnated at a mere one million users.

Further compounding this problem is the lack of a decent distribution channel. Some Web appliances are sold primarily via the Web, an odd channel for people who are buying the device to get their first Web access. Direct selling via print ads is possible but expensive, and selling technology conservatives a device they have never seen in person will be tough. That leaves consumer electronics stores, which are pathetically incapable of creating demand for new products or selling anything that requires significant explanation. (Another option is delivery through a service or e-commerce provider, which I discuss later.)

For all these reasons, I believe the successful early market for Web appliances (in the United States) will not be neophytes but experienced Web users who want additional access points. The likely buyer of a Web tablet is someone with one or more PCs who is an active Web user, and is increasingly likely to have a broadband connection to the 'Net.

Unfortunately, none of the early Web appliances is well suited to the Web aficionado. All sacrifice compatibility with significant portions of Web content because of the difficulty of providing plug-ins for all the popular formats such as RealAudio, Flash, and PDF, in a non-PC device. And that's just the beginning of the problems.

To keep costs down, Web appliances today must either use CRT monitors, which make them too bulky to fit easily into home dÈcor, or LCD displays. Alas, LCD displays introduce their own issues. First, they are expensive, thanks in part to a shortage of LCD production capacity. To keep costs reasonable, appliance designers typically choose lower-quality passive displays, which don't look nearly as good as typical PC displays (either a desktop CRT or a notebook LCD). Sometimes they compromise resolution as well. The result is a product that makes walking back to the den to use the home PC seem more attractive.

Price points present another big problem. Conventional wisdom is that consumer electronics devices above $500 are difficult to sell in large volumes, and that $299 and $199 are the magic points at which volume really takes off. A quality Web appliance can't attain these price points today unless the cost is subsidized by a service contract the approach most suppliers are taking. Commit to $20 a month for a few years, and you can buy the device in question for $199. This is a good strategy for the new Web user, but for the Web enthusiast market, where the early customers are most likely to be found, having a second ISP forced on them will generate a lot of resistance. This is especially true if you try to sell someone who already has a broadband connection a device that works only with a dial-up modem which is the case with all Web appliances introduced so far. With no pervasive standard for home networking, it is hard to build an appliance that can use broadband connections.

Does this picture seem rather dismal? I'm afraid it is, at least for the near term. I don't have high hopes for any Web appliances introduced so far, and I don't expect to see any successful Web tablets this year. Most Web appliances will first have to be established as additional access devices for existing Web users, which means they must deliver a high-quality experience and not compromise compatibility. They must integrate with existing broadband connections and provide access to existing printers, which requires home networks that aren't yet widely deployed and for which several rival standards are competing. Meeting these requirements raises costs, however, and using the customer's existing ISP service eliminates the major source of subsidy, so achieving acceptable price points will be difficult. For the next two or three years, new Web users are unlikely to find a better alternative than buying a cheap PC with preloaded Internet software and a bundled ISP. PC makers should focus relentlessly on delivering low-end PCs that come preconfigured as Web appliances, hiding all the PC complexity. Companies building Web tablets and other general-purpose Web appliances should focus on the enthusiast market; when these devices mature, after a few years of being sold to enthusiasts, and LCD costs fall, they will finally be able to attack the late-adopter markets that the PC will not have served yet.

In the near term, Web appliances may be most successful as access devices for particular services. Some e-commerce sites or financial services firms will offer heavily subsidized appliances to their best customers, giving the customer a physical portal. Broadband ISPs may provide subsidized appliances, just as phone companies once provided telephones. It remains to be seen, however, how many businesses will be able to justify the subsidy, and how many consumers will want the appliances if they don't address all the issues previously described. Web appliances may also be attractive in developing countries that are just now building an information infrastructure.

The most interesting Internet appliances will be those devices that aren't just another way to browse the Web but go further, audio players that get music from the Internet, kitchen appliances that scan bar codes and can place orders at WebVan, and so forth. Devices that fulfill a specific desire are more likely to succeed than those that aim at mimicking PCs. Like general-purpose Web appliances, however, these devices will take time to mature, consumers take time to warm to new product categories. Furthermore, device costs must come down, and Internet-delivered services must improve in quality and availability. Eventually, there will be a large market for Internet appliances, but developing that market will require careful targeting, patience, and persistence.

EEMBC Observations: Part II Analysis and Mysteries

By Markus Levy {9/25/00-02}

Part 1 of this two-part article series opened the Pandora's box on the EEMBC benchmarks and examined the finer details of the benchmark scores published on the EEMBC website. We presented the processor and compiler vendors with our observations about their products and scores and revealed a wide range of interesting architectural and compiler differences. The processors that we compared ranged from low-end 16-bit microcontrollers to the high-end 64-bit MIPS microprocessors. Part II presents the theory, analyses, and guesses from the vendors. Some of these differences were easily explained, some still remain a mystery.

EEMBC's benchmarks represent a wide variety of workloads. In particular, we observed that the benchmarks stressed the processor's floating-point capability, multiply performance, cache utilization and efficiency, and memory bus bandwidth. The benchmark scores were derived from EEMBC's out-of-the-box method, so we were also able to observe some interesting, and still unexplainable, compiler performance differences. Things will start to get more interesting when the remaining EEMBC members start to publish scores, it will allow us to make more apples to apples comparisons. But in the meantime, the exercises discussed in this article allowed MDR to begin sorting through the complex task of embedded processor benchmarking. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2000/0925/143902.html).

*** Embedded Tidbits ***

By Mark Long {9/25/00-04}

C-Cube Unveils SOC for Digital STBs

C-Cube has unveiled a chip for digital set-top box (STB) manufacturers that integrates multiple dedicated processing units, including a host CPU, A/V decoder, audio DSP, and graphics processor. The integrated 150MHz microSPARC CPU can act as host and supports applications like digital time shifting and soft modem. The AViA-9600 has both IEEE-1394 and USB ports for connecting digital cameras/camcorders, external hard-disk drives, DTVs, and printers to the STB. An IDE controller is also included to provide a direct connection to hard-disk drives to permit time shifting. In addition, the AViA-9600's MPEG decoder is equipped with multiple play modes that will allow STB users to pause, review, and fast-forward video programs stored on a hard disk. The AViA-9600's A/V decoder is fully compliant with DSS (DirecTV) and the DVB broadcast standard, as well as DVD and DES encryption. The chip offers support for 5C copy protection for the secure distribution of content over IEEE-1394. It also offers CPRM-based (Content Protection for Recordable Media) encryption for copy protection of content stored on hard-disk drives. The AViA-9600's audio DSP can process multiple audio formats, including MPEG-2, Dolby Digital. and DTS. Samples of the AViA-9600 will be available beginning next month, with volume production set to commence in 1Q01. Volume pricing for the AViA-9600 in a 308-BGA package will be less than $22 per unit. For more information: www.c-cube.com.

Motorola Intros High-Security Processor Family

Motorola has unveiled a family of information security processors that offer support for Bulk Data and Public Key encryption. The MPC180 and MPC180e have been designed to offload the processing of IP Security Protocol (IPSEC), Internet Key Exchange (IKE), Secure Sockets Layer (SSL), Wired Access Protocol (WAP), and Wireless Transport Layer Security (WTLS) protocols. Motorola's security technology has been designed to support performance up to 351 Mbit/s for the Triple Data Encryption Standard (3-DES) Bulk Data Encryption, and 363 Mbit/s on SHA-1 authentication.

The MPC180 offers Public Key performance with an expected signature time of 32ms for RSA supporting up to 13 IKE connections per second. In addition to the RSA support, the MPC180e offers Elliptic Curve Cryptography performance with an anticipated 11ms signature time that can process up to 45.5 IKE connections per second. Both the MPC180 and the MPC180e have been designed for integration into systems already using host, integrated, and network processors from Motorola. The devices feature a glueless interface to the local 8xx bus for the MPC8260, and also to the 60x bus operating at 50 and 66 MHz, respectively.

Packaged in 100-pin LQFP, the suggested price for the MPC180 processor is $16.25 in 10,000 unit quantities. Samples will be available in 4Q00. For the MPC180e, the suggested price is $20.25 for 10,000 quantities with samples also available in 4Q00. For more information: www.motorola.com/smartnetworks.

Motorola Reveals MPC7410 PowerPC Processor

Motorola has introduced a second G4 PowerPC microprocessor called the MPC7410 (MPR 10/25/99, "PowerPC G4 Gains Velocity"). Compatible with the entire PowerPC family dating to back to 1991, the MPC7410 is the first to be manufactured in the HiPerMOS 6 (HiP6) 0.18-micron copper fabrication process.

Like its MPC7400 predecessor, the MPC7410 supports full symmetric multiprocessing (SMP) capabilities for use in highly scalable and dense networking systems. In addition, the MPC7410 implements Motorola's high- bandwidth MPX system bus, capable of achieving data rates up to 6.4 Gbits/s. An L2 private memory mode allows system designers the choice of operating the processor's L2 cache as either a fast backside cache or as high-speed system memory. Software can also be optimized to utilize the Motorola's 128-bit AltiVec technology to help achieve performance gains for signal processing as well as to enhance host processor functionality (MPR 5/11/98, "AltiVEC Vectorizes PowerPC").

The MPC7410 PowerPC microprocessor is available in versions running at 400 MHz, 450 MHz and 500 MHz. The suggested list pricing is $95, $135 and $195, respectively, in quantities of 10,000 units. For more information: www.motorola.com/smartnetworks.

Silicon Spice Intros Communications Processor

Silicon Spice Inc. has introduced CALISTO, a single-chip communications processor for carrier-class voice gateways, soft switches, and remote-access concentrators/remote-access servers (RAC/RAS). The new chip, says Silicon Spice, replaces up to 10 traditional DSP discrete components, achieving more than 400 channels/in.2 while consuming less than 10mW per channel. The CALISTO (for configurable algorithm-adaptive instruction set topology) chip has been designed to manage a variety of DSP and packet-processing tasks, including echo cancellation; voice/fax- and data- modem signal processing; packetization; delay equalization; and telephony protocols within packet-telephony applications. The chip architecture reportedly provides more than 3.3 GMACs of signal-processing horsepower and 1.4MB of high-speed memory, which translates into 240 packet-telephony channels on a single chip. According to Silicon Spice, CALISTO's RTOS enables voice and data service providers to dynamically provision CALISTO for Any Service Any Port (ASAP) configurations ranging from 240 channels of carrier-class G.711 packet telephony to 60 channels of full Universal Port. Featuring a 239-pin BGA, the CALISTO device is augmented by an IDE that includes an Optimizing C Compiler and Multiprocessor Debug Environment. Currently sampling, CALISTO will be in full production by the end of the year. For more information: www.silicon-spice.com.

Hyperstone Unveils Integrated RISC/DSP Microcontroller Core

Hyperstone AG has launched a 32-bit microcontroller that features a RISC architecture with integrated DSP support, 16K of on-chip static RAM and options for low-power operation. The 180-MHz E1-32XS core combines both RISC and DSP functions in a single processor that communicates via a 96-way 32-bit internal register set.

The E1-32XS offers a power efficiency of 3.6GOPS/W, achieved through the parallel operation of three functional blocks of the integrated core: the RISC ALU, the DSP Unit and the Load/Store Unit. Instructions can be streamed simultaneously through all three functional blocks to deliver a peak performance of 720 MOPS.

The E1-32XS also incorporates several low-power consumption mechanisms. In the Power-Down Mode, only the interrupt logic, clock, timer and DRAM-refresh logic remain active. Sleep Mode additionally disables refresh of the external DRAM. At 2.5 V, current consumption in power-down and sleep modes is reportedly less than 2 mA and 100 µA, respectively. The integrated PLL function is also software-programmable to manage power consumption by slowing the internal clock frequency. Also featured: an on-chip DRAM controller that interfaces to external memory, allowing the designer to program page size, refresh rate, timing, and access parameters by using on-chip memory registers. The controller supports SDRAMs as well as fast-page-mode and extended-data-out DRAMs. Each of five external memory blocks can be supported with independent timing and bus width. The on-chip hardware timer is coupled to the clock via a programmable pre-divider from 2 to 257, running at speeds of up to 90 MHz with a resolution of about 10 ns for interrupt generation. Using the Hyperstone hyRTK kernel, the designer also reportedly has access to 254 independent, virtual timers with very low processing overhead.

The Hyperstone E1-32XS will be available in a 144-pin LQFP beginning in 4Q00, with volume pricing set for less than $8. The E1-32XS core IP will also be available under license. For more information: www.hyperstone-ag.com.

AMD Intros Embedded Processor Families

AMD is previewing two embedded processor families for use in tethered Internet appliances, set-top boxes, server networks and thin-client PCs. The AMD-K6-2E+ processor family integrates the 128K L2 cache and 64K internal L1 cache. Features include AMD's 3Dnow instruction set (MPR 6/1/98, "3Dnow Boosts Non-Intel 3D Performance") with five additional digital signal processing (DSP) instructions and a 100-MHz front-side bus. The AMD-K6-IIIE+ processor family offers support for the 256K L2 cache and the 64K L1 cache. Other features include the 3Dnow instruction set with five additional digital signal processing (DSP) instructions and a 100-MHz front-side bus.

Low-power versions of both processor families operate at core voltages ranging from 1.4 to 1.8 V, with power dissipation as low as 3 W, while standard-power versions operate at a core voltage of 2.0 V. In addition, all low-power processor versions feature AMD's PowerNow technology for reduced power dissipation. AMD says that PowerNow combines software and hardware support to enable the company's low-power embedded devices to run at different frequencies and voltages.

The AMD-K6-2E+ and AMD-K6-IIIE+ processors will initially be available in 321-pin PGA packages. Selected versions of the embedded processors also will eventually be made available in 349-lead organic ball grid array (OBGA) packaging.

Standard-power AMD-K6-2E+ processors will be available in 1,000 unit quantities at $78 (500 MHz), $71 (450 MHz) and $66 (400 MHz), while low-power versions will be priced at $82 (450 MHz), $76 (400 MHz) and $71 (350 MHz), respectively. The standard-power AMD-K6-IIIE+ processors will be available in 1,000 unit quantities at $101 (550MHz), $91 (500 MHz), $83 (450 MHz), and $78 (400 MHz), while low-power versions will be priced at $106 (500 MHz), $94 (450 MHz) and $89 (400 MHz). For more information: www.amd.com.

Cirrus Debuts High Security Maverick Processor

Cirrus Logic Inc. has introduced the Maverick EP7312 processor, a device based around a 74-MHz ARM720T core (MPR 11/15/99, Cirrus Logic Makes Music With ARM") that is destined for use in Information Appliances that require enhanced security technology for safeguarding digital content from unauthorized access. The EP7312 has been designed to store and process specific hardware IDs, such as those assigned for Secure Digital Music Initiative (SDMI) or any other authentication mechanism. Through the use of a security technology called MaverickKey, a permanent SDMI specific 32-bit ID and a 128-bit permanent random ID can be programmed into the device through the use of laser probe technology.

Cirrus claims that having these unique IDs on-chip provides more robust security than typical systems where these IDs would be outside the chip. In addition, MaverickKey allows the most sensitive part of security firmware to be executed on-chip for added security. The Maverick chip also incorporates hardware and software protection against unauthorized invasion by "locking" the chip from the inside out with the "keys" inside.

Beyond security, the latest Maverick processor improves upon its predecessors by featuring an upgraded SDRAM memory controller, 10K more on-chip SRAM, and Improved Digital Audio Interface (DAI). Designers can use the extra 10K of SRAM to further optimize the processor's internal code. The DAI provides an interface to DACs and ADCs by supporting both 128 and 64 fs bit rates. The processor's ability to directly support different audio sampling rates has also been enhanced. With production scheduled for 1Q01, the EP7312CV is priced at $19.35 and is packaged in a 208-pin Quad Flat Pack (QFP). Development Kits starting at $1,295 and samples of the Maverick EP7312 are available now. For more information: www.beamaverick.com.

Broadcom Announces E-Commerce Security Processor

Broadcom Corporation has announced the BCM5820 CryptoNET, a processor chip that the company says dramatically accelerates the processing of secure e-commerce transactions over Internet Information Servers running Windows 2000. A single BCM5820 processor can reportedly sustain up to 1,000 Public Key (1,024-bit RSA) transactions per second. Multiple chips may also be added onto a single PCI card, as well as onto multiple PCI cards installed within a single system, to scale any BCM5820 enabled server to handle thousands of RSA transactions per second.

The BCM5820 reduces all the required functions into a single 256-pin TBGA chip, with no external components or memory required. The BCM5820 also reportedly accelerates the ARCFOUR, 3DES and DES symmetric algorithms and supports MD-5, SHA-1, and random number generation through a 32/64-bit, 33/66-MHz PCI 2.2 interface.

The BCM5820 is packaged in a 256-pin TBGA and will sample to lead customers beginning in October, with production quantities available in November. Sample quantity pricing is $200. For more information: www.broadcom.com.

NEC Intros Upgraded 64-Bit MIPS Processor

NEC Electronics has announced an upgraded version of its 64-bit MIPS RISC microprocessor that delivers 377 Dhrystone MIPS at 200 MHz (MPR 3/9/98, "NEC VR5400 Makes Media Debut"). The VR5432 features a 32-bit external bus, a dual-issue superscalar architecture, multimedia extensions, floating-point capability, a 64K cache and a 64-bit internal data bus. In addition, the processor's dual-issue superscalar architecture includes two symmetrical pipeline control and execution units capable of executing any combination of integer and floating-point instructions at an average of 1.7 instructions per cycle. Also available: two unified integer/floating-point units, a non-blocking load/store unit, a high-performance 32x32 multiply-accumulate unit, a vector unit supporting 8x8 single instruction multiple data (SIMD) operations and a branch unit.

An on-chip 64K cache (32K instruction, 32K data) offers faster access to frequently used operations and data. The cache, which is two-way set associative, supports features such as cache line locking and data pre-fetching as well as the write-back and write-through cache protocols. Packaged in a 208-pin PQFP package, the 200-MHz VR5432 processor is priced at $25 each in 10,000-unit quantities. Samples are available now, with volume production scheduled for the first quarter of 2001. A 167-MHz version is also available now at $20 each in 10,000-unit quantities. For more information: www.necel.com.

Hitachi Intros HARP Embedded Design Products

Hitachi Semiconductor (America) Inc. has announced SH-3 and SH-4 microprocessor products based on the hardware architecture reference platform (MPR 8/23/93, "Hitachi Previews First PA-RISC Processor"). Each HARP CPU board is equipped with either a 133-MHz SH-3 (SH7709A), a 133-MHz SH3-DSP (SH7729) or a 200-MHz SH-4 (SH7750) RISC processor. The HARP CPU board also includes memory, control logic and input/output capabilities such as CompactPCI and an input/output (I/O) expansion bus connector. Other platform features include SDRAM, flash memory and boot PROM; a 10/100 Mbit/s Ethernet controller; a Universal Serial Bus (USB), serial port and parallel ports; a JTAG debug connector; a 66-MHz system bus; and IDE support (SH-4 HARP CPU board only).

A system I/O personality board is also provided that integrates a HD64465 general-purpose companion chip, MQ-200 graphics accelerator and AC97 audio codec. The HD64465 has a 66-MHz bus, 32-bit access, two-channel Universal Serial Bus (USB) host controller, Universal Asynchronous Receiver Transceiver (UART), 10-bit ADC, two timers, parallel port, and audio codec interface (I/F). Also included: PS/2 ports, two PCMCIA slots, JTAG interface, 40 GPIO pins, interface to Hitachi H8 8-bit microcontrollers, fast IrDA (FIR), analog front end (AFE) interface for modem AFE chips, and pulse width modulator (PWM). The MQ-200 2-D graphics accelerator has 2MB of on-chip DRAM, as well as LCD and CRT controllers for simultaneous operation.

Available now, the US7709A-HRP1xA with SH7709A SH-3 processor, the US7729-HRP1xA with SH7729 SH3-DSP and the US7750-HRP1xA with SH7750 SH-4 processor are each priced at $4,375/unit. For more information: www.hitachi.com/semiconductor.

Tasking Tools to Support StarCore DSP

Tasking is optimizing its compiler with unique DSP-specific extensions to deliver a multi-core, debugging platform in support of multicore and multiprocessor applications based around the StarCore SC100 DSP from Lucent Technologies and Motorola (MPR 10/26/98, "StarCore Launches First Architecture"). Available beginning in 2Q00, the SC100 Tool Suite will offer a complete software development environment in support of SOC and ASIC implementations, VLIW instruction-sets and parallel-processing units.

In addition to offering powerful proprietary DSP-C language extensions such as fixed-point data types and circular buffers, the compiler will feature optimization techniques such as leaf-function handling, register caching, loop unrolling, unroll-and-jam, peep-hole optimizations, instruction mutation, prediction-sensitive register allocation, and software pipelining using iterated modulo scheduling. The compiler, which generates minimal overhead while mixing C and assembly, will also support user-specified calling conventions that call legacy assembly functions from C code.

Tasking's CrossView Pro debugger will offer multicore debugging, program profiling and graphical data analysis. In addition, the debugger will provide execution control of individual processors as well as processor combinations, handling cross-processor breakpoints in the hardware and allowing designers to test interprocessor communications. Tasking says that CrossView Pro will also manage differences in the data communications link, execution control, data access, trace facilities and core architectures of multicore, multiprocessor platforms. In heterogeneous systems, CrossView Pro will integrate previously separate debuggers into one system to offer execution control of processor combinations and provide scripting across debuggers. For more information: www.tasking.com.

Microprocessor Forum 2000
October 9-13, 2000
San Jose

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