Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Cary Snyder, Mark Long, David Carey, with Howard Curtis, Tom Hunter, and Bill Weigle

In This Issue:

• MicroDesign Resources Microprocessor Forum 2000 Oct 9-13
• A Wolf in Sheep's Clothing
• Embedded Tidbits

Microprocessor Forum 2000 October 9-13, 2000 San Jose Fairmont Hotel

NEXT WEEK!

As the Editor of Embedded Processor Watch, I would hate for anyone to miss the session on Trends in High-Performance Embedded Processors Markus Levy and I are presenting next Thursday in San Jose. However the session is very close to being SOLD OUT with fewer than 9 slots left.

I'm discovering all kinds of interesting embedded processor news that will be revealed to the public for the first time next week. Come ask the experts; A small example includes:

- How are configurable embedded processor cores doing? ARC Cores going public in the UK reveals significant news... Tensilica is ready to talk more public about its many successes... EEMBC benchmarks may be coming soon...

- Does the new Silicon Spice Communications Processor, CALISTO contain the Xtensa Core from Tensilica? Last week's EPW featured an Embedded Tidbit that states the Calisto chip architecture reportedly provides more than 3.3 GMACs of signal-processing horsepower and 1.4MB of high-speed memory, which translates into 240 packet-telephony channels on a single chip. A quote from Vinod Dham, President and CEO of Silicon Spice, said "I have surveyed all of the core solutions available from PowerPC to SPARC and MIPS, and found that Tensilica's configurable solution is clearly superior in flexibility and is ideally suited for high performance, low power embedded applications."

- Does anybody get it right the first time out? Transmeta readies for a major launch... Details on Altera's embedded processors in FPGA... Xilinx and IBM starting a PowerPC FPGA hybrid chip..

- Get breaking details on new chips and architectures from: AMD, ARC Cores, ARM Ltd., Centaur Technology, Hewlett-Packard, Hitachi, IBM, Improv Systems, Intel, LSI Logic, Micron Technology, Motorola, picoTurbo, Samsung, SiByte, STMicroelectronics, Toshiba, Vulcan ASIC Ltd., Xstream Logic, ZF Linux Devices and more.

So the bottom line is... There is significant embedded processor news and great technical content at this years Microprocessor Forum 2000!

It's almost too late to register -- For more information please visit our web site at http://www.mdronline.com/mpf Or call 1.800.527.0288

A Wolf in Sheep's Clothing

Teardown Analysis and Product Assessment of Sony PlayStation2

By David Carey, with Howard Curtis, Tom Hunter, and Bill Weigle {10/2/00-01}

Sony's PlayStation2 (PS2) enjoyed a widely publicized introduction in Japan, selling 980,000 units on the launch weekend in early March 2000. One month later, Sony reported sales of 1.4 million units. The Japanese government even imposed controls, since relaxed, on export of the PS2, because the graphics processing was "adaptable for missile guidance applications," and the machine would potentially make basic supercomputer-level performance too abundantly available.

Beneath the surface, PS2 represents a vehicle for Sony to advance its invasion of the home and stake a claim in the merger of 'Net-centric computing and entertainment. PlayStation2 charts a path toward the future of networked digital entertainment. Just as PlayStation brought interactive gaming to an unprecedented mass market, PlayStation2's combination of breathtaking digital graphics, superb sound, and DVD video will open the way to a new computer-entertainment experience in the home. In Sony's view, PlayStation2 becomes the home server, while handheld game machines, such as Nintendo's Gameboy, serve as mobile clients. Ultimately, even one's cellphone becomes a game-machine client. Sony seeks to breathe new life into the debate over where and how home computing and entertainment will intertwine.

Product teardowns can provide much more than parts counts; they can form the basis for monitoring technology deployment, manufacturing strategies, design choices, and production costs in leading-edge systems. This article reflects Portelligent's approach to building system-level intelligence on key products that are shaping the future of personal and consumer electronics. Our teardown analysis of the PlayStation2 shows massive levels of engineering at the silicon and system levels. By some accounts, a weapons-grade supercomputer has been unleashed on the living room.

Certainly, Sony has achieved cost-sensitive refinements of high-performance packaging, high-speed electrical design, and thermal management. At a strategic level, the PS2 testifies to broad trends affecting the personal- and consumer-electronics industry. The machine threatens the hegemony of traditional PC-based home computing. It cloaks the capability of a home server for broader applications in the guise of a user-friendly game box. And it is affordable. For the long term, Sony is not so much selling a platform as it is subsidizing an infrastructure for content, where the war will ultimately be waged.

Embedded Tidbits

By Mark Long {10/2/00}

Intel Intros Internet Architecture

Intel has introduced its Personal Internet Client Architecture (PCA) for developing advanced applications for Internet-ready cellphones and other wireless handheld devices. PCA, unveiled at the latest Intel Developer Forum in Japan, specifies a set of interfaces between the hardware and software components of a wireless device, simplifying the system development process.

Intel reports that PCA will allow applications to be written for a variety of microprocessor architectures, although the one Intel has in mind is clearly the newly introduced XScale processor. Intel is also delivering Integrated Performance Primitives for StrongARM and XScale processors that will eventually enable designers to develop applications that can be ported to run on any Intel processor.

Intel's avowed goal is to establish an open, scalable architecture that fosters development of Internet services across all standards, protocols, and devices and also accelerates growth of wireless content, m-commerce (mobile commerce), and enterprise applications among wireless users worldwide. A preliminary specification detailing the scalable architecture has been distributed to key wireless companies, with a final specification and software developers kit scheduled for release by the end of the year. For more information: www.intel.com.

Motorola Unveils 150-mips Audio DSP

Motorola is playing its latest Symphony (see MPR 1/31/00-06, "Motorola's Symphony Plays Digital Music") with the release of a 24-bit, 150-mips audio DSP chip featuring the same memory map and peripherals as the company's previously released DSP56362 and DSP56366 chips. Motorola reports that the DSP56367 chip offers increased performance over its immediate predecessors in a pin-for-pin compatible device with a core that operates at either 1.8V (150 mips) or 1.5V (100 mips) for reduced power consumption. The DSP56367's typical power rating is 0.6mW/mips at 1.8V and 0.4mW/mips at 1.5V. For use in portable information appliances such as MP3 players, the chip needs approximately 22 mips for MP3 decoding, with the MP3 decoder using about 13.2mW at 1.8V and 8.8mW at 1.5V, respectively. Motorola says that systems may also be designed to clock the DSP at higher rates to permit features such as MP3 encoding on the same portable platform. In addition, Motorola claims to have future devices that will operate at 1.2V and 1.0V on the product roadmap.

Motorola's latest Symphony chip has been designed to process Dolby Digital, DTS, MPEG2 Multichannel and AAC, and DVD-audio, along with Dolby Headphone. Up to 100 mips may be allocated to other audio-processing requirements, such as subwoofer management, sound-field effects, 3D virtual surrounds, equalization, THX+Surround EX, DTS-ES, Prologic II, and Pacific Microsonics HDCD. The price for the DSP56367 is under $15 in quantities of 50,000. Samples, development tools, and documentation are expected to be available in early 4Q00, with volume production expected to commence in 1Q01. For more information: www.dspaudio.motorola.com.

Bay Claims Optical Development Role

Bay Microsystems has announced that it intends to develop and manufacture single-chip network processors for optical networks, broadband access gateways, voice gateways, and the datacom infrastructure. Launched in 4Q99 through funding from Selby Venture Partners, Alliance Venture Partners, and Needham Capital, Bay Microsystems says its next-generation network processors will provide a migration path from OC12 to OC48 and beyond. The company claims its initial chip will be able to sustain a guaranteed line-rate performance of 10Gb/s. Shortly after the release of its first chip, Bay says it will launch a 20Gb/s processor, followed by a 40Gb/s device. For more information: www.baymicrosystems.com.

Atmel Intros DAB Baseband-Processor Chip

Atmel has released a one-chip baseband processor based on an embedded OAK DSP core (MPR 8/1/94-01, "DSP Cores Bring New Levels of Integration") that features on-chip channel and source decoding for Digital Audio Broadcasting (DAB) applications. The U2739M completes Atmel's DAB front-end chip set, which provides all the analog and digital functions of a DAB receiver.

In accordance with the ETS 300 401 specification, the advanced CMOS-based U2739M demodulates and decodes the DAB bit stream at 1.82Mb/s (max). In addition to the audio source decoder (which supports ISO MPEG 1 and 2 layer 2), the chip features a data decoder that provides two independent packet-delivery modes and several standard interfaces, including I2C/L3, I2S, and RDI. Software modules may be replaced or extended by using a special boot mode. Time and frequency synchronization modules, for example, can be replaced by downloading the corresponding user-software algorithms to the OAK DSP core.

Samples of the U2739M are available now, and volume pricing is $24 each in quantities of 100,000. Atmel also offers a complete DAB evaluation kit that includes the RF front-end evaluation board, an interface board with microcontroller and A/D converter, and a baseband evaluation board. For more information: www.atmel-wm.com.

MIPS, Ampro Announce Agreement

MIPS Technologies and Ampro Computers have announced a broad technology, design, and marketing agreement to accelerate both development and deployment of MIPS-based systems for embedded applications. Under the terms of the multiyear agreement, Ampro will develop system modules based on MIPS32 processors that can function both as MIPS software-development platforms and high-volume OEM products. The new modules will be based on Ampro's EnCore platform, a processor-independent architecture for active-backplane single-board computers. According to Ampro, EnCore will be broadly supported by real-time operating systems (RTOS) and application software, and will be available to OEMs and software vendors for porting and development purposes. For more information: www.mips.com and www.ampro.com.

National Rolls Out Geode SOC Family

National Semiconductor has introduced a family of Geode (see MPR 8/2/99-03, "National Unveils 'Appliance On A Chip'") SOC devices for use in personal Internet-access devices, set-top box (STB) products, and thin-client networks. The SC3200 includes a Geode GX1 32-bit processor, a TFT video processor with a hardware video accelerator, three USB ports, core logic, and Super I/O functionality. Offering MMX support, the SC3200 integrates accelerated 2D graphics, a memory controller with 64-bit SDRAM interface and PCI bus, and display controllers. National claims that, excluding memory and the wireless communications subsystem, the Geode SC3200 provides all the capability needed to create a wireless WebPAD (personal access device).

The Geode SC1200 includes a Geode GX1 32-bit x86-compatible processor module, a TV video processor with four 10-bit video DACs, CCIR656 video-input port, IDE bus, three USB ports and a periphery of UARTs, and a Super I/O block. The SC1200 also offers MMX support, accelerated 2D graphics, a 64-bit SDRAM interface, and an internal PCI bus controller. The Geode SC2200 for thin-client networks, which creates thin-client desktop computing for networks operating from a centralized server, includes a Geode GX1 32-bit x86-compatible processor, a CRT and TFT display processor, core logic, and a Super I/O block. All three new Geode processors are manufactured using the company's 0.18-micron process technology and are priced at less than $50 each for high-volume applications. For more information: www.national.com.

Altera Intros Enhanced Tools for Excalibur

Altera has announced design-flow enhancements for its ARM- and MIPS-based Excalibur embedded processors, which are based on tools from the company combined with support from the existing ARM Development Suite (ADS) and third-party GNUPro tools. The Altera development tools include versions of Quartus and a new tool known as SOPC Builder. Altera's Quartus software supports system-level designs and features good-as-native links to third- party tools from Mentor Graphics, Synopsys, Synplicity, and other vendors. Quartus also features SignalTap, an embedded logic-analysis tool for in-system hardware debugging.

SOPC Builder is a front-end development environment that customizes and ties together both hardware and software for a given design. The designer can specify a wide variety of system parameters, which SOPC Builder then implements automatically, regardless of the processor core being used. The resulting hardware design feeds into Altera's Quartus development tools.

Software support for the new Excalibur devices will be available in the beta version of Quartus 2000.12, which will ship to customers beginning in October. The full Excalibur-enabled version of Quartus 2001.01 will be available early next year. Altera-specific versions of the ARM Developer Suite are available now. For MIPS designs, Altera will provide the complete GNUPro suite. For a $2,000 single-user license, an annual subscription entitles a customer to receive the latest version of MAX+Plus II and Quartus development tools, as well as all software updates for 12 months. For more information: www.altera.com.

S3, VIA Intro Merge Graphics, Core Logic

S3 Graphics and VIA Technologies have introduced an integrated graphics core-logic chip set that supports the Socket-A Duron and Athlon processors. The ProSavage KM133 is a shared-memory architecture (SMA) chip set that integrates the S3 Savage4 graphics core (see MPR 2/15/99-03, "Savage4 Shows Substantial Speedup") and features a 200MHz front-side bus with support for up to 2GB of PC133 SDRAM and VC133 DRAM. The complementary south bridge (VT8231) offers AC-97 audio, MC-97 modem, Super I/O and ATA-33/66/100 support, networking or Home PNA, four USB ports, and LPC (low pin-count) bus. The ProSavage KM133 is sampling now, with production set for 4Q00. The ProSavage KM133 is priced at $40 in OEM quantities.

The two companies have also announced release of the Twister core-logic chip set for mobile designs using Pentium III, Celeron, or VIA Cyrix III processors. The Twister north bridge features a 66/100/133MHz front-side bus with support for PC133 SDRAM, PC66/100 SDRAM, and VCM memory. Twister also uses the VT8231 south bridge chip. Twister is sampling now, with production set for 4Q00. Twister chips cost $35 each in quantities of 10,000. For more information: www.s3.com and www.via.com.tw.