Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Cary Snyder, Mark Long, Markus Levy, Peter Glaskowski, and Steve Leibson

In This Issue:

• SandCraft Declares War
• Lexra's RISC-DSP Core Power-Punches ARM9E
• PACT Debuts Extreme Processor
• Microchip "PICs" up RTOS Support
• EEMBC Expands Benchmark Options with Simulators
• Embedded Tidbits

SandCraft Declares War

Newly fabless, UMC ally targets QED and then SMP

By Steve Leibson {10/9/00-01} After changing its business model to become a fabless semiconductor vendor instead of merely a provider of MIPS-compatible processor-core IP, and after unveiling UMC as a foundry partner in September, SandCraft is now unrolling its ambitious battle plan for the next few years. This plan encompasses simultaneous forays across several different fronts and involves evolution of the company's existing SR1 core, along with development of two follow-on processor cores that will exceed gigahertz operating speeds.

Core development may, however, be one of the smallest skirmishes in SandCraft's plan. The company also plans to use the MIPS SysAD system bus for its first processors, but it will then drop SysAD in favor of AMD's LDT (Lightning Data Transport) bus. This move, coupled with SandCraft's intention of developing a high-speed on-chip multiprocessor connection fabric dubbed the Central Nervous System, will take the company squarely into the territory it wants to dominate: high-performance symmetric multiprocessing (SMP). (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2000/1009/144101.html)

Lexra's RISC-DSP Core Power-Punches ARM9E

MIPS Based Core Delivers 3x Performance at Half Power

By Cary D. Snyder {10/9/00-02}

The Lexra scalar LX5180 RISC-DSP core is a scaled-back, power-optimized version of the Lexra superscalar LX5280. Reducing features, as part of a power-conservation effort, may be the winning ticket for successfully competing in the tightly held, ARM-dominated embedded-processor market. Application-normalized power consumption and performance data suggest that the LX5180's mix of RISC and DSP functionality is ideally suited to compete in this market as an IP core for power-conscious system-on-a-chip (SOC) designs. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2000/1009/144102.html )

PACT Debuts Extreme Processor

Reconfigurable ALU Array Is Very PowerfulAnd Very Complex

By Peter N. Glaskowsky {10/9/00-03}

Combine the reconfigurability of an SRAM-based FPGA with a large array of ALUs and you get the potential for tremendous flexibility and performance. PACT's new Extreme Processor Platform (XPP) delivers that combinationóalong with some serious questions. The XPP architecture will be offered in chip form and as licensable IP for incorporation into customer chip designs. Although the IP-licensing business offers the best potential for future sales, PACT has to date focused on building a reference implementation of its architecture, the XPU128 processor chip. The XPU128 illustrates the potential of the architecture. The chip incorporates 128 processing array elements (PAEs), each of which can perform up to four 32-bit integer operations per cycle, each for a total of 51.2 BOPS at 100MHz. At 400mm2, the XPU128 is at the limits of the 0.21-micron process at PACT foundry partner Amkor, better known as a manufacturer of IC packages.

The XPU128 is real; the company is testing second-pass silicon that is expected to be fully functional. PACT has yet to implement an application on the XPU128 that realizes the full potential of the new architecture, but there is little doubt that such applications exist. The XPP architecture (named after a term coined by this writer) is a direct match for the needs of complex signal-processing algorithms. PACT simply hasn't had the time or resources to take a single application all the way to a complete implementation.

Discrete chips from PACT and its competitors fit into a relatively narrow market niche between the CPU and the ASIC. This niche may already be filled by the FPGA. PACT's pursuit of customers for the XPP architecture as an IP core seems to have a better chance of success. There may exist many more potential customers that could use just a small amount of reconfigurable computing in a device otherwise dominated by CPU and ASIC elements. Whether PACT can make a business of supplying IP or chips depends on how well the company can identify applications and develop products that meet customer needs. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2000/1009/144103.html )

Microchip "PICs" up RTOS Support

By Markus Levy {10/9/00-04} Realogy has just released RTOS support for Microchip's PIC18CXXX. It's difficult enough cramming a preemptive kernel into the limited on-chip memory space, but Realogy has added to that problem the challenge of dealing with a Harvard architecture. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2000/1009/144104.html )

EEMBC Expands Benchmark Options with Simulator

By Markus Levy {10/9/00-05}

Concluding an effort begun more than a year and a half ago, the EEMBC board has finally approved publication of certified benchmark results based on simulators. This measure allows members with intellectual property and preproduction silicon to publish scores anywhere (once they are certified). The consortium has imposed a long list of requirements for publication of simulator-based scores. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2000/1009/144105.html )

Embedded Tidbits

By Mark Long {10/2/00}

Alchemy Semiconductor Licenses Infineon DSP Core

Alchemy Semiconductor has announced that it has finalized an agreement with Infineon Technologies to license Infineon's Carmel DSP core architecture family. Carmel is a 16-bit, fixed-point DSP core with an architecture that operates at a maximum single-cycle instruction rate of 250MHz for up to 3,500 MOPS. (see MPR 12/28/98-04, "Carmel Enables Customizable DSP" http://www.mdronline.com/mpr/h/19981228/121704.html ) The agreement gives Alchemy rights to fully synthesizable versions of both the Carmel DSP 10xx and Carmel DSP 20xx core architectures allowing the company to both use and enhance existing Carmel high-performance and low-power attributes. The Austin-based fabless manufacturer says its acquisition of rights to Infineon's Carmel technology was the next logical step for Alchemy in rolling out products for the 3G data device, VOIP phones and gateways, and VODSL devices and gateway markets. Alchemy and its customers are currently in discussions to define the next-generation processors that will include the Carmel core. For more information: www.alchemysemi.com.

ARM, Verisity Intro AMBA Compliance Validation Products

Verisity Ltd. and ARM have announced development of two validation products for ARM-core-based systems: an AMBA Compliance Testbench (ACT) and an AMBA e Verification Component (eVC). ARM has developed ACT to check for compliance to the protocols associated with the AMBA on-chip bus specification. As a member of Verisity's Pure IP program, ARM will deliver the ACT as an Invisible Specman toolkit that can be used in a wide range of simulation environments.

The AMBA eVC is a preverified, reusable piece of verification code that customers can drop into their designs to achieve functional verification of AMBA-bus-based systems. The AMBA eVC joins the other plug-and-play modules that Verisity offers, including Ethernet, PCI, and USB. The ACT will be available from ARM in 4Q00, with pricing determined by specific customer requirements. Also available in 4Q00, the AMBA eVC will have a starting price of $10,000 for a one-year floating LAN license.

Rise, Acer Announce Multimedia Platform

Rise Technology and Acer Laboratories Inc. (ALi) have announced a multimedia platform for Internet set-top boxes (STBs) that features an iDragon mP6 microprocessor and ALi's Aladdin V chip set. The platform includes the Aladdin V M1541 north bridge, the M1535D+ south-bridge, and Rise's iDragon mP6 x86 microprocessor, which features on-chip power management and three-scalar multimedia architecture, which Rise claims boosts the performance factor for multimedia applications.

The Host Signal Processing (HSP) software interface in the M1535D+ south bridge and the iDragon mP6's multimedia architecture enable the software modem. The M1535D+ also provides integrated I/O interfaces, such as the ATA 100, AC-Link, SPDIF, USB, and SIO, for further system cost reduction. The M1541 north bridge supports a 100MHz bus. For more information: www.ali.com.tw and www.rise.com.