Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Steve Leibson, Cary Snyder, and Kevin Krewell

In This Issue:

• SH-Zam! SH Map Leads to SH-7
• Embedded Processor World War
• Sun Shines on UltraSPARC III

SH-Zam! SH Map Leads to SH-7

Hitachi, ST Reveal Additional SH-5 Details

By Steve Leibson {10/16/00-02}

In the comics, Billy Batson transformed himself into Captain Marvel by uttering the word Shazam! Hitachi and STMicroelectronics appear to have used that particular spell to transform the 32-bit SuperH processor into a 64-bit multimedia machine called the SH-5. The corporate duo first disclosed plans for the SH-5 at last year's Microprocessor Forum. The scalar, single-issue SH-5 executes all 208 instructions of its 32-bit SuperH predecessors. These existing instructions are actually 16 bits long and are now labeled the SHcompact instruction set. The SH-5 also executes 209 additional instructions, called the SHmedia set, which are 32-bits long and include SIMD and floating-point instructions. The LSB of the SH5's program counter serves as an instruction-set mode selector.

At this year's Microprocessor Forum, ST and Hitachi provided additional technical details on the SH-5 core design and a roadmap that extends the SuperH series an additional two generations, to the SH-6 and SH-7. The extra technical detail provides a deeper understanding of the SH-5 pipeline and virtual cache architecture. The seventh-generation SuperH processor takes the processor family well into the gigahertz realm. The processor core is taping out now. SH-5 partners Hitachi and STMicroelectronics are not yet saying when we can expect the SH-6 and SH-7. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2000/1016/144202.html )

Embedded Processor World War

Action Heating Up on Multiple Fronts

By Cary D. Snyder {10/16/00-01}

The opening salvo of Altera's Excalibur embedded-processor battle is not swordplay but a bold declaration of war. The expected end-of-year barrage will be a very capable $2,000+ (100-piece quantity) EPXA10 FPGA embedded-processor hybrid device shipping by the end of the year. The first Excalibur FPGA embedded-processor device is an ARM9-based embedded-processor stripe crafted to a million-gate Altera APEX 20KE1000E FPGA. It will be closely followed by a similar MIPS32 4Kc-core-based million-gate FPGA. Smaller, less costly devices of both processor camps will ship in 1H01.

Altera is likely to gain a significant lead over Xilinx in offering serious hard and soft FPGA embedded-processor hybrids. Xilinx's own PowerPC embedded-processor architecture has yet to debut in an actual product announcement that contains details on what IBM PowerPC core will be used or any other product details (see MRP 9/18/00-01, "FPGA Processor Cores Get Serious"). Altera's own PowerPC product announcement and details of a licensing agreement with Motorola are slow in coming, a hint that licensing issues between Motorola and IBM are complicating related agreements.

In the meantime, PowerPC may lose some interesting opportunities. Altera's Excalibur family creates interesting battlegrounds for easy performance evaluation of MIPS and ARM processor architectures with similar features in pin-compatible FPGA embedded-processor hybrid chips and other soft-core applications. Another important related area will be the emergence of the favorite on-chip bus: will it be the open ARM AMBA bus, IBM's CoreConnect, or something else?

All the action in the serious FPGA embedded-processor arena that is hosting soft cores, on-chip buses, and hybrid devices is quickly heating up battles in the embedded-processor market. Today's battles for whatever becomes the favored SOC design methodology or process will push the greater innovations of tomorrow. The embedded-processor industry is showing signs that everyone in these hard-fought battles can be a winner by making a profit, like a golf tournament in which everyone finishes in the money. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2000/1016/144201.html )

Sun Shines on UltraSPARC III

By Kevin Krewell {10/16/00-04}

Sun Microsystems has finally released the first of a series of UltraSPARC III-based products. It is now three years since Sun first revealed details of the UltraSPARC III at Microprocessor Forum '97 and about a year later than UltraSPARC III-based systems were expected to ship. In those three years, Sun raised the top target frequency at launch from 600MHz to 900MHz (which will be available in 4Q00). Sun also changed the main memory interface bus, widening it from 128 bits to 256 bits of data plus 32 bits of ECC.

In the first of three stages of UltraSPARC III-based product releases, Sun announced the Sun Blade 1000 workstations and the Sun Fire 280R small server. These announcements included only single- and dual-processor (SMP) configurations; large server configurations will be announced in 1H01. Sun announced shipments of 600MHz and 750MHz Sun Blade and Sun Fire products, with 900MHz products to follow in 4Q00 when Sun's fab partner, Texas Instruments, converts the 0.18-micron process (used to fabricate the UltraSPARC III processor) from aluminum interconnects to copper. In the aluminum process, the UltraSPARC III die measures 15.5mm by 15.9mm (246mm2), and in the copper process, the die size shrinks to 14.3mm by 14.7mm (210mm2). The 900MHz-based Sun Blade 1000 workstation has posted very competitive SPEC numbers of 438 SPECint2000 (base) and 427 SPECfp2000 (base), a major leap forward from the anemic performance of the aging UltraSPARC II family. Sun also revealed an outline of its processor roadmap, with UltraSPARC III processors scaling up to 1.5GHz; followed by the UltraSPARC IV processor, starting at 1.8GHz in late 2002; and leading to UltraSPARC V in late 2003, running at 2.1GHz. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2000/1016/144204.html )