Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Markus Levy and Mark Long

In This Issue:

• ColdFire V4 Gets Even Hotter
• Embedded-Tidbits

ColdFire V4 Gets Even Hotter

Enhancements to V4 Core Include 32 x 32-bit MAC, FPU, and MMU

By Markus Levy {10/23/00-02}

With the inclusion of the V4e extensions, Motorola's ColdFire architecture is almost on a par with the capabilities of the sentimental favorite 68K. The extensions, which were disclosed at this month's Microprocessor Forum 2000, include a floating-point unit, an enhanced multiply-accumulate (EMAC) unit, and a virtual memory-management unit. The V4e's FPU is a double-precision implementation of the MC68060 FPU that uses 64-bit registers instead of the MC686060's 80-bit registers. The EMAC, although backward- compatible with the original ColdFire MAC, is approximately twice as fast. The most obvious improvement of the EMAC is its ability to perform either 16 x 16-bit or 32 x 32-bit, single-cycle MAC operations. The V4e's MMU is a performance downgrade from that of the 68K, but it is a world ahead from a flexibility standpoint and uses a software-managed TLB (translation lookaside buffer) with support for 1K, 4K, 8K, and 1 MB page sizes. These new options give the V4 ColdFire a big boost and prepare the architecture for its move to superscalar. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2000/1023/144302.html )

Embedded Tidbits

By Mark Long {10/24/00}

ST, Hitachi Announce Super-H Developments

STMicroelectronics has announced the availability of its first SOC device based on a SH-4 RISC CPU Core that it has developed in partnership with Hitachi. (see MPR 10/28/96-08, "Hitachi SH-4 Gets Graphically Superscalar" http://www.mdronline.com/mpr/h/19961028/101408.html )

The 32-bit ST40-STB1, which has been designed to function in tandem with a variety of companion chips developed by the company, integrates a 66MHz PCI interface, a dedicated memory interface, a peripheral bus, 2 UARTS, parallel I/O, timers, DMA, and clocks. The 372-pin BGA device offers speed options of 150, 166, and 200MHz while delivering 360 mips and 1.4 GFLOPS.

Hitachi and STMicroelectronics have also announced their intention to codevelop next-generation Super-H architectures that will be compatible with the SH-5 architecture jointly announced by the two companies in October 1999. Slated for introduction in 2H02, the SH-6 architecture is expected to operate at up to 1GHz and deliver more than 2 GIPS performance. For more information: http://www.st.com.

Tensilica Announces Xtensa Processor Initiatives

Tensilica and Virtual IP Group have developed an MP3 audio decoder for Tensilica's Xtensa configurable microprocessor architecture (see MPR 3/8/99-02, "Tensilica Bends to CPU Designers' Will" http://www.mdronline.com/mpr/h/19990308/130302.html ).

The decoder offers hardware extensions and optimized code for accelerating MP3 decoding. Object code for the MP3 decoder is available now for license from Virtual IP Group under license fees starting at $30,000 for a single-instance use.

Tensilica Inc. has also licensed Dolby Digital AC-3 digital audio coding technology from Dolby Laboratories, Inc., to enable its customers to implement Dolby Digital within a single-core microprocessor equipped with specific instruction extensions to accelerate decoding. The Dolby Digital package for the Xtensa processor will be available in 1Q01.

Virtual IP Group Inc. has also released a 128-bit AMBA 2.0 compliant bridge for Xtensa that provides Ethernet, PCI, UART, USB, and memory controller interfaces. Delivered as synthesizable Verilog, the AMBA bridge can be licensed now from Virtual IP Group under a fee structure that starts at $35,000 for a single-instance use. For more information: http://www.tensilica.com.

ST Adds To x86 SOC Family

STMicroelectronics has added three new devices (called Consumer-II, Atlas, and Elite) to its STPC family of x86 PC-compatible SOC devices for embedded applications. Fabricated in 0.25-micron technology, each SOC contains a 64-bit, 133MHz processor block with an SDRAM controller that supports data-transfer rates of up to 720MB/s, a bus-mastering EIDE controller, and a high-speed PCI local bus controller. The three devices employ a Unified Memory Architecture (UMA) that permits the same memory array to be used for both CPU main memory and the graphics frame buffer.

The clock speed of all three devices has also been increased to 133MHz, while power consumption has been reduced to 2.5W (Consumer-II and Atlas) or 1.5W (Elite). The Consumer-II and Atlas are equipped with a VGA/SVGA- compatible graphics accelerator, and the Elite offers a 16-line, general-purpose I/O block. The Atlas also incorporates standard I/O functions. Housed in plastic BGA packages, the Consumer-II and Elite will begin sampling in November, with volume production set for late 4Q00. The Atlas is also expected to begin sampling before the end of the year. The Atlas will be priced at less than $38, the Consumer-II at less than $33, and the Elite at less than $26 in 10,000-unit quantities. For more information: http://www.st.com.