Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Cary Snyder and Mark Long

In This Issue:

• Embedded-Tidbits
• The Microprocessor Report Seminars and Dinner

Embedded Tidbits

By Mark Long {10/30/00-05}

* Chicory HotShot Accelerates Java and Others *

Chicory's HotShot uses a silicon-based just-in-time (JIT) translation engine to compile languages such as Java into native processor instructions, thus speeding program execution by as much as a factor of 25. The technology can also operate on other nonprogramming languages, such as XML, and can even compress or decompress data packets using algorithms such as JPEG and MP3.

The HotShot translation engine uses an assortment of "pistons" that supply the engine with instructions for performing the translation. Each instantiation of the HotShot engine can have multiple pistons. In addition to the speed gained by hardware translation, Chicory reports that HotShot technology can decrease battery-power requirements for host code execution by up to 95% by performing the translation once and then saving and executing the translated code. For more information: www.chicorysystems.com.

* Hantro Joins MIPS Alliance *

Hantro Products and MIPS Technologies have announced a cooperative agreement under which Hantro is joining the MIPS Alliance Program (MAP) and integrating its scalable MPEG-4 codec with the MIPS32 4K family of processor cores. Available for licensing, Hantro's MIPS32-based media platform delivers video decoding and encoding at a rate of 15 frames per second. For more information: www.mips.com and www.hantro.com.

* Motorola Samples StarCore-Based DSP *

Motorola has begun shipping samples of the MSC8101, its first DSP to use the SC140 core architecture developed by the StarCore Alliance (see MPR 10/26/98-04, "StarCore Launches First Architecture" http://www.mdronline.com/mpr/h/19981026/121404.html ). The chip is implemented in a 0.13-micron copper interconnect process developed by Motorola's DigitalDNA Laboratories. With four ALUs providing 1,200 MMACS, the MSC8101 integrates a 150MHz CPM programmable network protocol engine, 512KB of on-chip SRAM, a 100MHz 32- or 64-bit PowerPC bus interface, and a programmable memory controller. Also on chip: peripherals such as a 300MHz enhanced filter coprocessor (EFCOP) and a centralized DMA engine. The MSC8101 is expected to be available in volume quantities in 3Q01 for less than $100. For more information: www.motorola-dsp.com.

* Motorola Unveils Embedded Automotive Processor *

Motorola has unveiled an embedded processor for automotive powertrain applications that includes 1.0MB of flash EEPROM memory. Built around a 56MHz PowerPC core with a floating-point unit, the MPC565 features 1MB of flash memory divided into two 512KB blocks, 46 KB of fast static RAM, a four-bank external memory controller, and on-chip peripherals such as three timer processor units (TPUs). Each TPU is a 32-bit microRISC engine capable of processing 28 million instructions per second. Vehicle networking is supported with three TouCAN (CAN version 2.0B) and one J1850 interface. Manufactured in Motorola's 0.25-micron embedded nonvolatile memory process, the MPC565's logic core operates from a 2.6V supply, whereas peripherals operate at voltages of up to 5V. The device is backward compatible with the MPC555, the earliest member of an automotive product line that was introduced in 1998. For more information: www.solutions.motorola.com.

* C-Cube Intros Integrated DVD Chip *

C-Cube Microsystems Inc. has introduced a DVD processor chip that includes an MP3 audio codec, progressive-scan video output, and embedded Internet applications. Built around the company's ZiVA architecture, the ZiVA-5 incorporates a 150MHz, dual-issue SPARC CPU with integer and DSP instructions. The ZiVA-5 also contains a 32-bit, 2D multiplane graphics engine and a TrueScan field-adaptive de-interlacer. In addition, the chip's programmable NTSC/PAL/480P video encoder offers support for both interlaced and progressive scan video and Macrovision AGC version 1.03 for 480P. ZiVA-5's 225-mips dual-audio-DSP architecture is capable of decoding MPEG-1 Layers 1 and 2, MP3, MPEG-2 5.1, Dolby Digital, Dolby ProLogic, DTS, HDCD, and MLP. The ZiVA-5 chip also includes multichannel Meridian lossless packing audio decode, LPCM audio decode, Copy Protection for Pre-recorded Media, audio watermark detection, real-time text insertion, and DVD-Audio disk navigation. The processor's audio encoder supports a variety of audio algorithms, including MP3.

Packaged in a 208-pin PQFP, ZiVA-5 chips will begin sampling later this year, with volume shipments set to begin in 1H01. For more information: www.c-cube.com.

* National Samples Next-Generation DVD Chip *

National Semiconductor Corporation is sampling a next-generation DVD chip based around a 32-bit MIPS II processor. Featuring a progressive- scan NTSC/PAL video pipeline operating at up to 108MHz, the Mediamatics NDV8501 integrates all the normal video and audio functions of a DVD player--including host processing, video and audio processing, I/O function, and video DACs--into a single chip. In addition, the NDV8501 offers an on-chip SCART interface in full compliance with European TV standards. On the audio side, the NDV8501's custom 24-bit DSP supports all disc-based audio formats, including the Meridian lossless packing algorithm (MLP). In addition, the chip can decode DTS Digital Surround, MPEG-2 multichannel, and MP3 formats and can provide audio effects such as karaoke, 3D stereo surround, and Dolby Prologic through post-processing.

The NDV8501 chip is currently sampling at $30 per unit. For more information: www.national.com.

* ARM Launches Smart Card Processor Core*

ARM has unveiled the first of the company's SecurCore family of 32-bit microprocessor cores for the smart-card market. The SC100 includes the Thumb instruction set and an ARM memory-protection unit capable of performing secure MMU-type functions as well as a range of SPA/DPA countermeasures. (SPA/DPA means simple power analysis/differential power analysis, techniques used to crack processor-based security algorithms.) SecurCore releases will be licensed as IP cores for implementing ASIC or ASSP designs. Each synthesizable core also incorporates anticounterfeiting technology that ARM says will protect a card issuer's investment in silicon development without compromising security. ARM also claims that the core is designed to resist invasion and tampering at both the hardware and software levels. In addition, ARM announced the development of a new debug and test methodology, designed specifically for SecurCore devices, that includes a one-way development process for engineering on-chip security features. SecurCore releases will be available from ARM semiconductor licensees at prices based on the system-level design requirements of each customer. For more information: www.arm.com.

* Toshiba Licenses ARM946E-S Core *

Toshiba has licensed the ARM946E-S core from ARM in order to integrate the core with DRAM to produce SOC products for 3G wireless applications. Toshiba has also licensed the ARM Embedded Trace Macrocell (ETM9) for use in debugging its ARM946E-S-core-based offerings. Toshiba SOC devices incorporating the ARM946E-S solution are expected to be available starting in 1Q00. For more information: www.toshiba.com.

* Intersil Intros ARM-based Chip Sets for Wireless LAN *

Intersil Corporation is developing ARM-based media access controller (MAC) chip sets in support of the 2.4GHz IEEE-802.11b standard as well as 5GHz, 54 Mb/s chips based around the 802.11a standard. First out of the chute is the ISL3856, an 802.11am ARM9-core-based chip that has been optimized for use in wireless hubs and gateways. Intersil's ISL3856 MAC chip for 802.11b applications will also support mandatory data rates for 802.11a. In addition, the ISL3856 supports 128-bit encryption as well as 10- and 100Mb/s data rates through the chip's onboard Ethernet interface. Scheduled for introduction later this quarter, the ISL3856 chip set will be available for $19.20 in 10,000-unit quantities. The firmware, software, and radio reference designs for the ISK3856 will also be made available at the same time. For more information: www.intersil.com/prism.

* Parthus Launches Mobile Internet-on-a-Chip Platform *

Parthus Technologies PLC has launched a system on a chip for mobile wireless Internet devices. Using the Symbian EPOC32 operating system, the ARM 920T-powered InfoStream SOC operates at 200MHz at 2.5V or 150MHz at 1.8V, with processor speed set by adjustment of a configurable PLL. The Infostream SOC also includes a color LCD controller with a 40KB video frame buffer, a USB controller, a smart-card interface, a 10-channel DMA, and a 28-channel interrupt controller, plus three UARTs, three counter/timers, and a real-time clock. The InfoStream design employs clock-gating techniques that control processor power consumption. For more information: www.parthus.com.

* Atmel Licenses PalmDSPCore From DSP Group *

Atmel has licensed the PalmDSPCore from DSP Group for use in mobile communications SOC designs (see MPR 9/14/98-en, "VLSI Handles First PalmDSPCore"). Backward compatible with DSP Group's earlier TeakDSPCore and the OakDSPCore offerings, the PalmDSPCore offers seven arithmetic units working in parallel. Up to 18 operations can be executed per clock cycle for a peak performance of 3,800 MOPS (3.8 GOPS) at 210MHz in 0.18-micron CMOS technology. The core's instruction sets allow the device to execute an FFT butterfly in only two cycles and a Viterbi-decode in only two cycles per two Add-Compare-Selects (ACSs). For more information: www.atmel.com

.*** The Microprocessor Report Seminars and Dinner ***

What's next for Intel's microprocessor business?

What's the best way to choose among the many new high-performance embedded processors for home and office information appliances?

You can find out at two full-day Microprocessor Report seminars to be held on December 7 at the Westin in Santa Clara.

FULL DAY SEMINARS

"The Intel Microprocessor Forecast: The Challenges for the Future"
- Kevin Krewell, Microprocessor Report

Get an extensive look at Intel's x86 and IA-64 product roadmaps and the company's ability to follow them, given its fab capacity and structure. Based on MDR's proprietary model of Intel's production costs and capabilities, Mr. Krewell will disclose MDR's forecasts for Intel's processor performance, pricing, capacity, unit shipment, and cost trends through the end of 2001, plus forecast information through mid-2002.

"Trends in High-Performance Embedded Processors"
- Markus Levy and Cary Snyder, Microprocessor Report

Explore the technical merits of processors that deliver maximum processing speed in new information appliances for the home and office with Microprocessor Report Senior Analysts Markus Levy and Cary Snyder. This full-day seminar will provide in-depth analysis of the latest 32- and 64-bit architectures from all of the key industry players-including newcomers and long shots.

Please join us after the seminars for a special DINNER PRESENTATION on

"Next-Generation Lithography for Manufacturing Microprocessors"
by Chuck Gwyn, Program Director, EUV LLC.

REGISTER NOW! Space is limited for both the seminars and dinner, so reserve your place today. Complete seminar descriptions, plus pricing information and online registration is available on the at http://www.mdronline.com/december7/index.html, or give us a call at 800.527.0288 or 408.328.3900.