Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Cary Snyder, Steve Leibson, and Mark Long.

In This Issue:

• Intel-ligent I/O Processing
• Jesse Lipcon: Interview With a Pioneer
• Embedded-Tidbits

Intel-ligent I/O Processing

Trend Setting I/O Performance

By Cary D. Snyder {12/11/00-03}

Intel has dominated the PC processor market for years. It is now carefully maneuvering to become the dominant player in the embedded- processor market with products based on XScale and other outstanding components. Intelís first XScale product implementation is the new 80310 I/O processor chip set, which should prove to be a trendsetter in its own right. The IOP310, as the first product based on Intelís new XScale microarchitecture (see MPR 9/11/00, "XScale (StrongARM-2) Muscles In"), appears to play well using a proven component mixture: StrongARM, i960 I/O processors, and the de facto PCI-to-PCI bridge standard. Intel is likely to succeed in becoming an ascendant I/O processing player with a recipe of best-in-class components combined into its new I/O processor chip sets. There are two chip sets to start: the Intel IOP303 chip set as a single i960-based chip (signaling a future single-chip direction) and the IOP310 chip set based on the 80200 processor chip and the 80312 I/O companion chip.

Success of the IOP310 chip set is virtually guaranteed by its inclusion of features and capabilities that are part of tested I/O processing architectures. Best-in-class components are the XScale processor core, the next generation of the StrongARM processor; i960 I/O processing features; and a highly regarded PCI-to-PCI bridge core. Integrated functional blocks include special I/O modules like performance monitoring, an I2O messaging unit, an I2C I/F, a DMA controller, and Intelís user-programmable 512B-to-1KB Application Accelerator. Intel plans to target a wide range of I/O processing applications in the Internet storage arena (SCSI, Fibre Channel, Storage Area Networks [SAN]), networking (LAN, ATM, Ethernet, switches, routers), and various high-performance embedded applications.

The single-chip I/O processor trend that Intel is setting with these products is important in the evolution and integration of embedded microprocessors that specifically target I/O processing applications. Motorola has the MPC8240 (see MPR 11/16/98-en, "Motorola PowerPC 8240 Gets PCI Bus"), its own single-chip PowerPC 603e integrated processor chip that can be used as an I/O processor. And in the middle of next year, IBM will be shipping its 400MHz PowerPC 440GP integrated processor chip, which could find its way into I/O processor applications. This chip and other I/O processor architectures occupy the same functional space as Intelís IOP303/310 chip sets but have less integration and fewer I/O-specific features. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mpronline.com/mpr/h/2000/1211/145003.html)

Jesse Lipcon: Interview With a Pioneer

Digital's Veteran Designer Reviews the Last 28 Years of Computer System Design

By: Steve Leibson {12/11/00-02}

Jesse Lipcon joined Digital Equipment Corporation in 1972, just after Intel introduced microprocessors to the world. Since then, he's worked on computer system design teams, using microprocessor implementations of Digital's architectures from the PDP-11 to Alpha. Lipcon retired from Compaq (which bought Digital) on November 17, 2000 to do some volunteer work and to pursue interests in consulting with start-up companies. He remains a consultant to Compaq as well. What follows is an edited transcript of an interview with Lipcon on his last day as a Compaq employee. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mpronline.com/mpr/h/2000/1211/145002.html)

Embedded Tidbits

By Mark Long {12/4/00-03}

National Licenses Xtensa from Tensilica

Tensilica has announced that National Semiconductor has licensed the company's Xtensa III IP processor core. (See MPR 06/19/00, Vector DSP, FPU Extend Xtensa) National will employ the technology to develop configurable microprocessor cores for the high-speed Ricochet modem technology it is developing in concert with Metricom. For more information: http://www.tensilica.com/technology.html

ARC Intros Bluetooth IP Core

ARC Cores has announced BlueARC, an intellectual property (IP) core for use in wireless devices based on the company's Tangent-A4 microprocessor as well as in a baseband controller and protocol stack from Tality Corporation (MPR 11/20/00-02, "FPGA Processors Ready For Take Off"). The BlueARC IP core includes HDL source code for the baseband controller. In addition, it offers integrated USB, Bluetooth profiles, a BlueRF-compliant radio interface, SoC design-support files, software-development and debug tools, and a BlueARC development system. BlueARC evaluation kits based on the ARCangel FPGA development system will be available in early 1Q01, followed by a full product release in early 2Q01. For more information: www.arccores.com.

Infineon Intros 16-Bit MCU Core

Infineon Technologies has announced the release of the C166S V2, a microcontroller core optimized for SoC applications requiring an embedded control architecture that can perform digital-signal processing tasks in real time. Manufactured using the company's 0.18-micron logic-based embedded DRAM process technology, Infineon's C166S V2 core delivers a scalable performance at clock frequencies up to 200MHz. The C166S V2, which is capable of executing most instructions within one clock cycle, is based on a core that is instruction compatible with all previous C166 microcontroller releases. In addition, the C166S V2 integrates a MAC unit into the core's FPU, allowing the core to execute a FIR filter with one tap per cycle.

Developed jointly by Infineon Technologies and STMicroelectronics, the C166S V2 core will be available for open licensing in 2001. For more information: www.infineon.com.

Motorola Unveils Flash-Based MCU

Motorola has unveiled the MC9S12DP256, the first in a family of flash- based 16-bit microcontrollers for automotive network applications. The MC9S12DP256 contains six multiplex network modules that implement either the CAN or J1850 communications protocols. Nicknamed the "Automotive Super Gateway," the MC9S12DP256 and its derivatives use Motorola's 0.25-micron embedded split-gate flash (SGF) technology for data retention and write-erase cycling on 256K of flash memory and 4K of long-word erasable EEPROM. The microcontroller also features 12KB RAM and true 5V I/O, together with integrated peripherals such as two eight-channel 10-bit A/D converters, and eight PWM channels. In addition, the device offers three SPI ports, two SCI ports, one IIC port, and an eight-channel timer. The MC9S12DP256 is sampling now, with volume production set for 2H01 at a price of less than $10 in high-volume quantities.

One Square Inch Ethernet Web Server

NetMedia, Inc. has announced their SitePlayer SP1 Web Server Coprocessor Module that is not much bigger than a postage stamp. In it you get a 10baseT Ethernet controller, microcontroller with the alphabet soup of protocols, Ethernet downloadable flash web pages, and firmware updates, and an object system for making live graphical displays. You give it 5 Volts, it gets an IP address from a DHCP server (or static) and you surf it. Communications with SitePlayer is through a serial port to send and receive data from any device processor. 18 pin device mounts on standard 0.1" headers. SitePlayer is made to web enable new or existing devices, or be used as a plug-in option. $29 in 100 pieces. For more information: www.siteplayer.com.

Scenix Crosses the Ubicom With 10Base-T

Ubicom (the new name for the microcontroller vendor formerly known as Scenix) has unveiled the first part in its IP2000 family of network- oriented Harvard-architecture RISC microcontrollers. Processors in this family have an 8-bit data word and a 16-bit instruction word. The 100MHz IP2022 costs only $13.30 in 10,000-unit quantities but includes 64K of flash instruction EPROM, another 16K of instruction SRAM, and 4K of data SRAM. (The device can't access off-chip memory.) Like the previous SX microcontrollers from this vendor, the IP2022 uses its high execution speed to implement peripherals in software. IP2000 peripherals include a 10Base-T Ethernet controller (using an on-chip hardware serializer/deserializer), a USB port, a UART, an I2C port, and an SPI port. In addition to the serializer/deserializer, the microcontroller has other on-chip hardware peripherals, including two 16-bit timers and an 8-bit A/D converter with a 10-channel input multiplexer. The company also provides software modules, including a TCP/IP software stack to support the Ethernet controller. The four-stage pipelined processor core is capable of single-cycle execution from the instruction SRAM but the flash EPROM has a 40ns access time, so execution from the flash instruction memory slows the execution rate. The IP2022 operates on 2.5V and has an on-chip charge pump to allow in-circuit flash memory programming. For more information: www.ubicom.com.