Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Cary Snyder and Markus Levy.

In This Issue:

• Topic of the week: The Coming Era of Field Programmability
• ARM Embraces SIMC Support
• Embedded Tidbits

Topic of the week: DesignCon 2001
By Cary D. Snyder

"The Coming Era of Field Programmability (Or are ASICs dead?)" was the title of Chuck Fox's Keynote Presentation today at DesignCon 2001. Chuck, President and CEO of Chameleon Systems, made a compelling argument for why the traditional ASIC - or rather the traditional ASIC design process - will perish under current time-to-market pressures. I had to agree; we are entering a "chip-on-demand" age where increased system programmability is the only way to solve the time issue.

The System-on-Chip Conference Panel, aptly titled "The ASIC/FPGA Battle: Will a Hybrid Solution Win?" concluded that indeed a hybrid FPGA and ASIC will ultimately win the battle. Panel member Ronnie Vasishta, Sr. Director of Technical Product Marketing at LSI Logic, said that the biggest issue with today's ASIC design flow is verification and that adding FPGAs to ASICs enhances the flexibility of system verification. Chris Balough from Triscend said that getting a product to market quickly is more critical than ever, especially at the edge of the communications infrastructure. Fellow panel members, Peter Feist from Quicklogic and Bruce Weyer from Xilinx, both agreed that hybrid devices would play a critical role in meeting their customers' needs. Bruce made a good point that most customers want to squeeze as much bandwidth as possible into a 26 1/2 inch wide rack.

Traditional embedded-microprocessors have fixed interconnect and are programmable by the ISA. Periodic software programming changes have become a common way of providing equipment flexibility. The key requirement of the communications market - meaning LAN, WAN, wireless and telecom applications - is to increase system flexibility, and this drives the need for more system configureability.

ARM Embraces SIMD Support
By Markus Levy {01/02/01-03}

<Rerun with Title Correction>

ARM's SIMD instructions, albeit a little late in coming, will give the company's architecture a big performance boost for DSP and multimedia applications. The new instructions focus on a variety of operations, including multiply-accumulate, add, subtract, rounding, saturation, and select. Although specific implementation details haven't been released, it appears that the company will accomplish these instructions with minimal hardware additions and without changing the architecture's programming model. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mpronline.com/mpr/h/2001/0102/150103.html )

Embedded Tidbits
By Cary D. Snyder

* Hitachi, Triscend Partner On Programmable Chip *

Hitachi and Triscend have partnered to jointly develop a configurable system-on-a-chip (CSoC) based on Hitachi's SuperH 32-bit RISC microprocessor. The SH2 processor, using Triscend's Configurable System Logic (CSL) matrix, will be manufactured by Hitachi using their 0.18-micron technology. The product is aimed at the cost-sensitive telecommunications market and should go into volume production sometime in 2002. The major goal is to develop a low-cost SH2 processor with the configurable attributes required by an increasing number of developers. Privately-held Triscend manufactures chips based on 8051 and ARM7TDMI processor cores. This should be a good move for both companies with Triscend making a small investment to leverage its software and hardware IP into a new market and Hitachi providing its customer base increased flexibility at a decreased cost. (For more information see http://www.triscend.com or http://www.hitachi.com)

*XILINX REFERENCE DESIGNS FOR EMBEDDED PROCESSORS*

According to Xilinx, providing embedded-processor reference designs will speed development of systems with high-performance embedded processors. These new reference designs are for IBM PowerPC, Intel StrongARM and Pentium-class, and QED processors. They target the Xilinx Virtex and Spartan series FPGAs as a part of the Xilinx Empower! program that is part of Xilinx's Platform FPGA initiative. Using FPGAs as companion chips in high-performance embedded-processor systems is a common design implementation choice, and Xilinx customers should benefit from this endeavor.

The most pronounced benefit is that programmable attributes of the FPGA provide additional freedom in choosing custom embedded-processor features. Using FPGAs in this manner provides increased control for engineering trade-off among elements of system performance, system power, and system design.

General performance and bandwidth capabilities for these interfaces, including processor speed, bus speed and width, and burst bandwidth are provided on the Xilinx Web site. For example, a reference design for interfacing multiple PowerPC 60X processors, including the bus arbiter and protocols, SDRAM, and flash memory controllers is shown implemented in Virtex-E or Virtex-II FPGAs.

A StrongARM design and development kit that implements 32-bit/33MHz PCI and 100MHz SDRAM interfaces for Intel's StrongARM SA-1110 processors using the 100,000-gate Spartan-II FPGA is available through Xilinx's distribution partner, Avnet Electronics.

Other common high-performance embedded applications can use a Virtex-E or Virtex-II FPGA as a companion chip for an 850MHz Pentium or 250MHz QED RM7000A processor. A Pentium design using the Spartan-II family is also available.

Another detail on the previously announced IBM-Xilinx project is that a hard-core PowerPC 405 microprocessor from IBM will be embedded in the Virtex-II architecture. This core is slated to operate at a 300MHz clock speed and to offer more than 420 Dhrystone mips of performance. Additional details on how the PowerPC 405 core supports a peak communications bandwidth of more than 6GB with the FPGA fabric will be provided in an upcoming Microprocessor Report article. (See www.xilinx.com or www.avnet.com for the StrongARM development kit from Avnet Electronics.)

* EDA Tools Optimized for New Altera Architectures and Quartus II Development Software *

Altera Corporation has announced a major update to its synthesis and simulation tools from third-party EDA vendors that support Altera's newest architectures: the APEX 20KC device family and the Excalibur embedded- processor solutions, which incorporate ARM-based and MIPS- based embedded-processor cores. These new versions of third-party EDA tools provided by Mentor Graphics, Synplicity, and Synopsys are optimized to work seamlessly with Altera's recently announced Quartus II development software. Altera claims that the new Quartus II development software establishes a new standard for PLD software, providing designers with an advanced environment for system-on-a- programmable-chip (SOPC) design.

Altera says it has been working closely with its key EDA partners to include innovative synthesis and simulation algorithms in their software to support Altera device architectures, especially Excalibur embedded-processor solutions. In addition, all the companies have worked together to improve the integration of these EDA tools with Altera's new Quartus II development software to provide Altera's customers with the best possible system-on-a-programmable-chip design experience.

According to Mentor Graphics, the Excalibur embedded-processor solutions and APEX 20KC devices begin a new era in programmable logic devices. Exemplar, in close collaboration with Altera, has enhanced Mentor's FAST (FPGA Architecture Specific Technology) algorithm in LeonardoSpectrum to take full advantage of these new architectures for the benefit of mutual customers.

A spokesperson for Synplicity Inc. indicates that the company's Synplify product integrates seamlessly with Altera's advanced Quartus II development software, producing excellent results for the APEX device families and the Excalibur embedded processor solutions, including significant compile-time improvements.

Synposys indicates that its FPGA Express OEM version 3.5.1 includes support for Altera's latest products, including the new Excalibur embedded-processor solutions and the APEX 20KC family of devices and works in a tight flow with Altera's new Quartus II development software. Because of close cooperation between Altera and Synopsys, the version 3.5.1 release of FPGA Express and FPGA Compiler II includes several features to ensure high-performance quality of results (QoR) in the diverse applications that use the latest Altera architectures. For example, Synopsys' advanced algorithms significantly reduce the logic needed to implement constant coefficient multipliers.

ModelSim provides Altera customers with simulation performance; behavioral, RTL, and gate-level simulation capability; and a debug environment on all current popular platforms. All standard ModelSim products, along with the ModelSim Altera Version, available directly from Altera, can be used with the new Quartus II development software to develop designs for the complete Altera product line, including Excalibur embedded-processor solutions and APEX 20KC devices.

Pricing and Availability

The new versions of the Mentor Graphics, Synplicity, and Synopsys tools are available in February 2001. The Altera OEM versions of LeonardoSpectrum, FPGA Express, and ModelSim will be available in February 2001 from Altera for all new subscriptions and as an upgrade shipment for all existing customers on active subscription. At $2,000 for a single-user, PC-based license, an annual subscription entitles a customer to receive the first version of Altera's Quartus II development tool and the latest version of Altera's MAX+PLUS II development tool and the Mentor and Synopsys OEM synthesis and simulation tools, as well as all software updates for 12 months. For more information see http://www.altera.com.

* XILINX SHIPS INTELLECTUAL PROPERTY FOR VIRTEX-II FPGAs *

Xilinx has announced the availability of new, enhanced intellectual property (IP) cores for use with the Xilinx next-generation Virtex- series FPGAs. Xilinx claims the Virtex-II devices provide designers "with a programmable platform to more easily integrate with both soft and hard IP cores." Xilinx discussed Virtex-II devices and the cores at the XtremeDSP/Virtex-II Technical Simulcast at the Santa Clara Marriott Hotel on January 25, 2001, in a presentation that was broadcast live via satellite to movie theaters in 45 North American cities. Details of this simulcast can be accessed at http://www.xilinx.com/events/seminars/xtremedsp.htm.

AllianceCORE partner Kevin Heawood of NMI Electronics claims that Virtex-II devices give FPGAs a major step toward meeting true system- level characteristics. According to Mr. Heawood, the "Virtex-II device not only has more logic resources, more memory, and faster routing, it also incorporates sophisticated clock and impedance management. These latter features are just as critical to the design of real-world systems as raw logic and memory. We are already incorporating the Virtex-II devices into our MicroEngine Single Board Computer family."

The Xilinx AllianceCORE program has more than 20 third-party IP providers developing and enhancing cores for use in Virtex-II devices. Products in development include a DSP development board and cores that support embedded- processing and networking applications. An important performance parameter that was mentioned comes from AllianceCORE partner ARC Cores (UK), which achieved a 60% speed increase in its 32-bit configurable processor core ported into a Virtex-II device.

Xilinx claims that the latest IP release for Virtex-II devices includes new and enhanced cores, such as an 8-bit/10-bit encoder and decoder, parameterized synchronous and asynchronous FIFOs, and a single- and dual-port block memory generator. The release also includes cores that are part of the Xilinx XtremeDSP initiative (see November 21, 2000 press release), such as a FIR filter generator, parameterized multiply and accumulate (MAC), and a multiplier generator. (For more information see http://www.xilinx.com).