Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue:Max Baron, Cary D. Snyder, Peter N. Glaskowsky,
and Markus Levy.

In This Issue:

• Editorial: Transformers
• Xilinxís A-to-Z System Platform
• ARM Displays Imagination
• Embedded Tidbits
• MDR Seminars and Dinner on March 15, 2001

The following departments have been updated in the Microprocessor Report:

• Patent Watch
• Literature Watch
• Chart Watch
• Resources

To access these articles, just go to http://www.MPRonline.com and enter your User ID and password.

Editorial: Transformers

Some transformers have cores made of powdered ferrite, iron, or air; some are impedance-matching baluns; and some even rotate. The Transformers that concern us, however, are those that can be purchased from Toys "R" Us. Not the electric-train type either. We are thinking of the expensive, garish, rocket-driven beasts--destroyers using laser guns, death rays, ion thrusters, missile launchers, rotating turrets, and Xtor pellet-spraying weapons.

Remember them? Defenders of the galaxy, these megafighter robots can be converted into additional forms. One form may be a two-wheeled motorcycle suitable for attack. A second form, a six-wheeled vehicle for carrying supplies or performing strategic retreats--when confronted by more powerful (and more expensive) beasts. They are expensive. Some Transformers are mechanically complex; you have to be, if you need to convert your wheels into feet, your motorcycle into a body, and, as a robot, stand up and shoot red plastic missiles. Transformer benefits seem to transcend the pain of paying the price: children and collectors get three toys for the price of two. A kid, going out to play, may take only two Transformers: six toys that, wisely employed, will be equal to any situation.

It is interesting to note that the same approach is now seeing a rising popularity in digital consumer appliances. Polaroid's PhotoMAX MP3 is a digital camera that, in addition to a lens and other accessories, comes with earphones. The camera can play songs compressed in MP3. USB helps it upload pictures and download music. Kyocera's Smartphone Series QCP looks like a Palm organizer with a microphone and earpiece; it is a cell phone, organizer, and browser all in one. Casio sells a watch that plays MP3 music, another that takes pictures, and a third that lets you record short voice memos. Makes engineering sense--it does share expensive resources. And yes, some of these products come in colors as garish and shapes as strange as those of the toy Transformers.

Not to be left behind, microprocessors have started to play the same game: one processor can emulate other Instruction Set Architectures (ISA). Transmeta's Crusoe is an interesting combination of hardware and morphing software that brings to mind a broader spectrum than the execution of IA-32 binaries. Software-based Java interpreters and JIT compilers make the case for emulating a virtual machine on top of any processor. And an additional software product coming from Transitive Systems Ltd. in the U.K. has found a way to create native instruction-set binaries from code compiled for other processors. Transitive Systems is using trace-driven interpreters/compilers to obtain application- and user-optimized native code. Software, be it trace-driven, morphing, or interpreting, is Transformer-like: different software for different translations. The end user can switch software. It can be application triggered.

Many applications require dedicated hardware for satisfactory performance. Hardware transformers are more difficult. Microprocessors fighting for survival have become like the toy Transformers, bulging with added coprocessors, instruction sets, patches, and extensions. ARC and Tensilica have gone one step further by enabling embedded-system engineers to add their own specialized instructions. Designers can now fine-tune an ISA to the particular needs of the application. Improv and Infineon have introduced designer-configured DSP devices. But, unlike software, the new offerings, once cast in silicon, are impossible to change.

Configurable chips may be able to improve the scenario. Some use high- frequency microprocessor cores to emulate custom functional blocks. Others use on-chip microprocessor cores and programmable logic devices (PLD). Still others use a hybrid approach involving microprocessors, DSP, ASIC, and PLD resources. All are configured via some form of memory that ships with the product.

Makers of configurable chips are touting the advantages to both semiconductor and system vendors. Fewer different components are needed, because designers can customize them. They are more expensive, but they help lower the inventory risk in a roller-coaster-ride industry. To the end user, configurable chips offer the somewhat nebulous promise of upgrades via telephone or the Internet.

But there is a glimmer of hope. In-circuit programming has to be supported for upgrades. A few million flip-flops can be programmed in fractions of a second from local flash memory, the size of which is increasing as fast as its price is going down. The transformer engine is near. A new type of platform is evolving with increasing PLD frequency, density, and the addition of microprocessor cores. It may quickly instantiate and send back to memory DSP engines, coprocessors, logic blocks, software applications, device drivers, and even operating systems --adapting itself to the end-user, peripherals, or connectivity needs. Complete hardware-software minisystems might be downloaded from the Internet as tryouts or rentals-- to expire after a given time or continue as permanently present, purchased configurations. It may all depend on the price point of the new transformers and on the definition of the robot's body and that's up to you.
By Max Baron {02/26/01-01}

Xilinxís A-to-Z System Platform

Looking for SoC Architectural Strength?
By Cary D. Snyder {02/26/01-02}

System-on-a-chip (SoC) designers are getting more help and options from a nontraditional source--programmable logic vendors. Altera will ship its PLD with an embedded ARM processor next quarter and is promising a similar MIPS- processor-core version shortly after (see MPR 10/16/00-01, "Embedded Processor World War"). In addition, details are emerging on a competing product, Xilinx's new Virtex-II and its next-generation processor hybrid architecture.

The challenge for Xilinx FPGA designers was to meet all the requirements for a next-generation FPGA or PLD 'system-friendly' architecture. The task appears monumental when one analyzes typical system or SoC requirements. The long list of new features and process changes suggests that complete success with a single product jump is difficult--perhaps impossible.

It is apparent that Xilinx has had the luxury of starting from scratch on multiple design fronts with its new Virtex-II Platform FPGA families. An attempt to list all the possible architectural features of Xilinxís Virtex-II and next-generation FPGAs conducive to SoC design on a macro scale is likely to fail--there are too many possible application variations. A minimum architectural analysis of Xilinx's Platform FPGA capability is satisfied by examining three broad areas: processor, DSP, and bandwidth capabilities-- all essential to successful SoC designs.

Xilinx is not close to shipping an FPGA with an embedded processor; however, Virtex-II is positioned well as a companion chip (see MPR 2/12/01-03, "Xilinx Pushes for Companion Chip Role"). Xilinxís next-generation Platform FPGA will embed a hard-core PowerPC 405 microprocessor from IBM directly in Virtex-II- type FPGA fabric. This new family will use Virtex-II-type Active Interconnect technology to implement IBM's CoreConnect as an on-chip bus supporting 6GB-peak bandwidth to the FPGA fabric. Plans are likely to include a multi- processor version of the chip.

An analysis of the Virtex-II architecture isn't complete without a look at XtremeDSP capabilities, essential to emerging wireless and broadband standards. Bandwidth is a major part of the successful communications SoC picture, with Xilinx expending a great deal of effort to meet wide and fast on- and off-chip bus bandwidth. Architecture details and the flexibility they offer SoC designers will make for a very interesting year in embedded processors. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mpronline.com/mpr/h/2001/0226/150902.html).

ARM Displays Imagination

New Graphics Cores Bring 3D to Embedded Applications
By Peter N. Glaskowsky {02/20/01-01}

Embedded-processor vendor ARM has struck a deal with Imagination Technologies that will allow ARM to offer PowerVR graphics cores alongside ARM's processor cores. The two companies will develop two PowerVR cores one for low-power mobile applications, such as cell phones and PDAs, and a faster version aimed at line-powered devices.

The agreement will make it easier for ARM's customers to add graphics and video acceleration to their products. Other graphics cores are available from companies such as 3Dlabs, Bitboys, and Trident, but these companies do not focus on the embedded market. The new PowerVR cores will be optimized for the specific needs of their respective applications, making them easier to use and less expensive to implement.

Faster Core Suits Set-Tops

The faster PowerVR core will be similar to that used in Sega's Dreamcast video-game console. The new core will be designed to support standard- definition television displays up to 640 x 480 pixels in size, refreshed up to 60 times per second to match the capability of progressive-scan televisions. For interlaced displays, the core will include a video filter to eliminate flicker, and customers can request an MPEG-decoding accelerator option.

The PowerVR core is a good choice for embedded applications because of its relatively low memory-bandwidth requirements. The PowerVR architecture was one of the first to perform hidden-surface removal prior to final rendering, which greatly reduces memory accesses for Z-buffer (distance) tests and unnecessary pixel drawing (see MPR 3/5/96-04, "Competition Heats Up in 3D Accelerators"). Other 3D architectures use similar techniques today, but Imagination has considerably more experience with this optimization.

ARM expects that its customers will combine this core with ARM9 and ARM10 processor cores, using the AMBA on-chip bus to create integrated system-on-chip controllers for set-top boxes, Internet appliances, and similar systems. The ARM10 core is available with ARM's VFP10 vectorized floating-point coprocessor, which can complete a 32-bit floating-point multiply-accumulate operation in every clock cycle (see MPR 11/16/98-03, "ARM10 Points to Set-Tops, Handhelds"). (The full version of this article is available online to Microprocessor Report subscribers at http://www.mpronline.com/mpr/h/2001/0220/150801.html).

*** News Item ***

Actel Embeds FPGA Core in ASICs
By Cary D. Snyder {02/26/01-03}

Actel has announced that it will provide reprogrammable SRAM gate array cores to ASIC and ASSP designers. Called the VariCore EPGA (Embedded FPGA) IP Cores, the new devices will target application-specific integrated circuit (ASIC) and application-specific standard product (ASSP) systems on a chip (SoCs). Development started early in the summer of 2000 with formation of the VariCore business unit. Foundation technology and expertise came from acquisitions of Prosys Technology and GateField Corporation, which Actel purchased last year.

The VariCore EPGA cores increase the flexibility of SoC designs by helping to reduce design time and overall costs. The initial EPGA blocks have been designed for 0.18µm CMOS SRAM technology; they will be followed by smaller process geometries in future device generations. Targeted customers include users from the ASSP world using independent silicon foundries and ASIC suppliers that have their own IP portfolios.

Actel claims its VariCore EPGA technology has the smallest on-chip reprogrammable SoC die area available and a better performance/die-area ratio than standard FPGAs. The cores use standard ASIC design methodology and flow. Several major independent silicon foundries support the process. Proven VariCore programmable logic silicon has been completed at UMC and TSMC in Taiwan and at Chartered Semiconductor in Singapore.

In related news, Actel announced that it is joining UMC's Gold IP program with its VariCore embedded programmable gate array (EPGA) IP cores. Actel has taped out a VariCore EPGA IP test chip in UMC's 0.18-micron fab in Taiwan. UMC is adding VariCore embedded programmable logic cores to its Gold IP Program library.

Actel's new IP core fulfills the industry's current need for reconfigurable SoC ASIC/ASSP designs. The need is driven by the requirement to simplify adaptation to rapidly changing standards. At the same time, customers are asking for the flexibility to create multiple products from a single SoC device. VariCore EPGA blocks are, in essence, reprogrammable "soft hardware" core tiles.

The EPGA cores are based on a three-input LUT (look-up table) structure. Each PEG (primary embedded gate) block has 2,500 ASIC gates, with PEG blocks being scalable and configurable from a 2 x 1 EPGA of 5,000 ASIC gates up to a 4 x 4 EPGA core of 40,000 ASIC gates. In addition, the family's 4 x 4 and 4 x 2 members offer eight optional, cascadable RAM modules configuration of 1K x 9 or 512 x 18.

VariCore EPGA cores can handle system clock speeds of up to 100MHz, covering 75% of the reconfigurable requirements expected for ASIC and ASSP designs during 2001. In a 4 x 4 EPGA core utilized at 80%, VariCore EPGA cores reach the levels of performance noted above while maintaining 100-200mW power consumption, depending on core performance.

VariCore place and route is performed by the high-speed VariCore Compiler design tool and other third-party design entry, verification, and test tools. The VariCore Compiler supports VHDL or Verilog design entry in RTL-based design flows. Synthesis support is provided by Synopsys Design. Front-end design verification supports VHDL, Verilog, and Vital simulations and is also compatible with the Synopsys PrimeTime and PrimePower performance- and power- simulation tools. File output is in hard GDSII IP format that is compatible with Cadence's Virtuoso and Avant's Apollo. Physical design verification, layout versus schematic (LVS), and design rule checks (DRCs) are supported by Cadence's Dracula and Avant's Hercules II.

The production version of VariCore Compiler is now shipping. Pricing for VariCore EPGA cores will vary and will follow an IP sliding scale model of license plus royalties. Actel's Web site is at http://varicore.actel.com.

Embedded Tidbits

By Cary Snyder {02/26/01-04} and Markus Levy {02/20/01-02}

Toshiba's 200MHz TX4927 Ships
By Markus Levy {02/20/01-02}

Toshiba America Electronic Components, Inc. (TAEC) has announced the availability of its 64-bit TX4927 microprocessor. The Toshiba TX49/H2 MIPS processor core within the TX4927 is based on a five-stage pipeline with a 64-bit datapath. The core includes an MMU with a 48-double-entry TLB, four- way set-associative 32KB instruction and data caches, a hardware MAC, and a double-precision floating-point unit. The processor includes an SDRAM memory controller that can handle four channels of registered and nonregistered DIMM SDRAMs (100MHz maximum) with ECC. An external bus controller supports eight channels of ROM, flash memory, and memory-mapped I/O devices; a PCI bus controller supports either four 33MHz bus masters or two 66MHz bus masters. A DMA controller supports four independent channels plus one channel for specialized PCI; interrupt controllers capable of monitoring 18 different sources; two UART channels; three 32-bit timer/counter channels; and 16-bit bidirectional parallel-I/O ports.

The TX4927 microprocessor is built on Toshiba's 0.18-micron, 3.3V-I/O/1.5V- core process and comes in a 420-lead ball-grid-array package. Production quantities of the 200MHz version of the TX4927 are available now at $35 (in quantities of 10,000).

Tensilica Ups Ante in Core War

Tensilica announced that its Xtensa III processor is the first core technology to be certified by EEMBC, the embedded microprocessor benchmark consortium.

Tensilica engaged in a two-step certification process. The first involved benchmarking the basic Xtensa configuration the out-of-the-box score. The second step, designed to illustrate the significant improvements obtainable by adding designer-configured custom instructions to the base processor, involved tuning the default configuration through an iterative process, using Tensilica's proprietary Instruction Extension (TIE) compiler. Tensilica created three application-specific configurations one each for EEMBC's consumer, networking, and telecommunications benchmarks using the same methods customers routinely use to tune Xtensa processors for their designs. Each configuration ran at 200MHz and employed simulated 0.18-micron technology.

To make the benchmarking more meaningful to potential Xtensa processor designers, Tensilica engaged a Stanford University MSEE graduate student to perform the initial and fine-tuning of all device configurations, mimicking the learning curve typical for a new user. The student received a three-day instruction course before starting, the same basic training offered all Tensilica customers. Before this assignment, the student had no direct experience in microprocessor design.

In the telecom benchmark series, the final core was configured with an added Vectra DSP Engine to illustrate the performance gains possible through preconfigured add-ons. Total elapsed time spent optimizing three separate instances of the processor for all 11 benchmarks, including C-code optimization, was only 10 weeks.

Differences between the out-of-the-box core and the full fury results were significant, ranging from a 4x speed improvement after TIE configuration for the Packetflow algorithm in the Networking suite to a speed improvement of 830x for the Convolutional Encoder algorithm of the Telecommunications suite.

• Networking Benchmark Highlights: 2.4x performance speedup, 3% reduction in code size
• Telecommunications Benchmark Highlights: 225x performance speedup
• Consumer Benchmark Highlights: 122x performance increase with 18% reduction in code size (average improvement across the individual tests)

To find out more about EEMBC benchmarking, go to: www.eembc.org/benchmark.

TI's New DSPs Target 3G Apps

Texas Instruments recently unveiled three members of its new generation of programmable digital-signal processors (DSPs). Operating at speeds up to 600MHz, the new TMS320C6000 DSPs offer up to 10 times the performance of other available DSPs for broadband applications and up to 15 times the performance for advanced imaging/video applications.

The new TMS320C6414, TMS320C6415, and TMS320C6416 DSPs are the first devices based on the TI TMS320C64x DSP core. TI says that in addition to increased performance, the new products will also consume one-third the power of the older core. The company claims that this improvement maximizes channel density in communications infrastructure equipment, including 3G wireless base stations, digital subscriber line access multiplexers (DSLAMs), and other network concentration units.

According to TI, the new chips will also feature optimized system-level integration for reduced system costs and faster time to market, with complete high-level language development environment. The most highly integrated new device is the C6416, which includes coprocessors and input/output (I/O) interfaces specifically targeted at 3G wireless base stations. The C6415 integrates the same I/O interfaces, without the accelerators, for use in other broadband and imaging systems. The C6414 features general-purpose interfaces for systems that do not require dedicated network connectivity.

TI also offers a portfolio of high-performance standard linear Ics that support the C64x DSPs, including power- management ICs, plug-in power solutions, DC/DC converters, and supply voltage supervisors (see www.ti.com/sc/docs/msp/dsps.htm).

Initial sampling of all three devices is scheduled to begin in June 2001. TI plans to offer 400-, 500- and 600MHz versions of all the devices, all packaged in a space-saving 532-lead, 23 x 23mm ball-grid array (BGA). Planned pricing begins at $95 each for 10,000 units of the 400MHz C6414. Development tool support for the new C64x DSPs is available to qualified customers now and is scheduled to be available to the general market in June 2001. Technical documentation is available on the Internet at www.dspvillage.ti.com/newc64xdsps.

Kodak Uses TI DSP for Media Combo

The new Kodak mc3 combines a single programmable digital-signal processor (DSP) from TI and Kodak's imaging science to enable delivery of digital video, pictures, and music in one portable unit. The programmability of TI's DSP also provides the ability to upgrade the Kodak mc3 firmware, allowing it to record and play the latest audio and video formats--both present and future, according to Kodak. The mc3, introduced on February 13 at the DEMO 2001 conference and also featured by TI and Kodak at the Photo Marketing Association (PMA) International trade show, uses the same DSP core that brought TI success in powering portable Internet audio and digital imaging products. (See www.ti.com/sc/digitalcamera for more details.)

TI's programmable single-chip solution for the digital camera market, the TMS320DSC21 DSP, delivers multiple imaging and audio functionality. The Kodak mc3 can record video at either 20 frames per second for highest resolution or 10 frames per second for almost unlimited recording on its removable memory card. It also captures color still images in VGA resolution and can store 90 minutes of MP3 music on a 64MB CompactFlash memory card. TI's DSC21 supports interfaces for a microphone, speaker, audio output/headphone, video output, and USB for uploading and downloading files. The programmability of TI's DSPs also enables upgradability, allowing Kodak to offer continued support of new audio and video compression formats via software downloads at its mc3 user Web site (www.kodak.com/go/mcXchange).

Kodak's mc3 will be sold with 16MB of memory for $229 and 64MB of memory for $299 and is scheduled to be available in retail stores in March.

The DSC21 supports many popular digital audio and video formats, including real-time MPEG1, MPEG4, JPEG, MJPEG, H.263, and MP3, plus data communications standards such as IrDA, USB, and RS-232.

Motorola Joins Wind River Program

Motorola and Wind River Systems have announced that Motorola has joined Wind River's Center of Excellence program. The two companies signed a multiyear agreement to facilitate the development, optimization, marketing, and distribution of Wind River's embedded software products across Motorola's line of PowerPC microprocessors. With more than 80% market share, Motorola is the leading supplier of communications processors that enable customers to develop a wide range of products for next-generation networks. Wind River is a leader in embedded software and services for creating connected smart devices. This initiative will deliver optimized solutions when silicon first becomes available, allowing customers to leverage the latest advances in Motorola's silicon technology.

Using an off-the-shelf, integrated solution, customers developing products with Motorola's PowerPC microprocessors and Wind River's embedded software will, according to the participants, have the advantage of reducing costs and shortening development cycle times. The relationship illustrates Wind River's strategy for building relationships with semiconductor partners and Motorola's strategy of continuing alliances with third parties to deliver Smart Networks Platform solutions.

Through the Center of Excellence, Wind River and Motorola will establish joint engineering and marketing relationships for Motorola PowerPC-focused products. The first scheduled products from Motorola and Wind River's Center of Excellence are expected to include Tornado support for Motorola's MPC7410 and MPC7450 processors with delivery anticipated to begin in 1H01. For more information, visit Motorola's Web site at www.Motorola.com/smartnetworks and Wind River's Web site at www.windriver.com

Infineon Intros New Low-Power DRAM

Infineon Technologies of Munich, Germany, introduced a new DRAM product line on February 12. Intended for the strongly growing market of handheld devices, the Mobile-RAM family combines three important features specifically needed in handheld battery-powered applications: very low power consumption, small form factor, and low cost per bit.

The Mobile-RAM is a low-power SDRAM mounted in a chip-size ball-grid-array (BGA) package. Initially based on the 128Mb DRAM density, this product fulfills the requirements of handheld applications like smart phones, personal digital assistants, and palm-size computers. The 8M x 16 organization of the first member of the Mobile-RAM family allows it to be used in 16- and 32-bit bus environments.

Infineon claims that power consumption of the Mobile-RAM is reduced by up to 80%, depending on operating conditions and system design. This power reduction is achieved by a reduced operating and I/O voltage and other integrated power-management techniques.

The world market for personal digital assistants (PDAs), the largest of the target markets for the Mobile-RAM, was approximately 10 million units in 2000 and is projected to reach 34 million units in 2004. Today's high-end PDAs come with up to 64MB of DRAM, but memory content per system is expected to grow at more than the industry average.

First samples of the 128Mb Mobile-RAM organized 8M x 16 will be available in 2Q01. Volume production is expected to start later this year. For additional information about Infineon's product portfolio of DRAMs and modules, visit www.infineon.com/products/memory.

Micron Intros Low-Power DRAMs

Micron Technology earlier this month introduced the first devices in its new BAT-RAM family of low-power synchronous DRAMs (SDRAMs). Micron's new BAT-RAMs are designed to consume less power than standard SDRAMs and to extend battery life in many mobile and wireless applications. Micron is currently sampling 2.5V and 3.3V 2Mb x 32 64Mb BAT-RAM devices and will introduce next-generation devices later this year.

Micron claims its new BAT-RAM family cost-effectively provides the densities, organizations, and speeds critical for the battery-powered world. The BAT-RAM devices include a new feature, temperature-compensated self-refresh (TCSR). When enabled and programmed by the system, this feature allows the part to adjust refresh rate and power consumption on the basis of ambient temperature. At normal room temperatures, this feature allows the devices to consume even less power.

JEDEC, the leading semiconductor standards-setting body, is currently defining standards for low-power DRAMs, and Infineon is working on developing these standards. For more information about JEDEC or free access to JEDEC standards, visit the Web site at www.jedec.org.

Samples of 2.5V 2Mb x 32 BAT-RAM SDRAM devices (MT48V2M32LFFC) and 3.3V 2Mb x 32 BAT-RAM SDRAM devices (MT48LC2M32LFFC) are available now. More detailed information on component specifications is available from datasheets that can be obtained from Micron's Web site, www.micron.com.

STMicro Develops DVD-ROM SoC

STMicroelectronics recently announced that it has now produced the first wafers of the Indus system-on-a-chip (SoC) that powers DataPlay's micro- optical engine, the engine for DataPlay digital media, which won the Best Lifestyle Product award at January's Consumer Electronics Show in Las Vegas. DataPlay's digital media is a new small-format optical media solution developed for recording and distributing digital content for portable devices like music players, digital cameras, e-books, and games. A single 500MB disk, costing about $10, can hold more than 11 hours of music downloads or five complete CD-quality prerecorded albums, hundreds of high-resolution photographs, or dozens of games.

The drive for these disks is the DataPlay micro-optical engine. DataPlay chose STMicroelectronics to develop and manufacture the key Indus SoC IC that incorporates most functions of the engine. Containing two embedded processors and many other functions, this complex chip contains more than seven million transistors and will be produced in 0.25-micron CMOS technology.

ST finished designing the final version of this chip in 4Q00 and has now produced the first preproduction parts for delivery. Both ST chips are assembled in compact, low-profile ball-grid-array packages, so the complete drive is small enough to be built into portable products like digital cameras and handheld computers.

Samples and documentation for the Indus and Yukon ICs are currently available only through DataPlay. Equipment makers interested in adding DataPlay storage capability to their products should contact DataPlay at www.dataplay.com. Further information on ST can be found at www.st.com.

MDR Seminars and Dinner on March 15, 2001

Join Microprocessor Forum and MDR Chief Analyst Steve Leibson, MDR Senior Analyst Kevin Krewell, and EUV LLC Program Director Chuck Gwyn for morning and afternoon seminars and a special dinner presentation hosted by Cahners MicroDesign Resources.

- Morning Seminar:

Inside Todayís PC Processors: Architectures, Microarchitectures, and Performance

presented by Kevin Krewell, senior analyst, Microprocessor Report, and editor, Microprocessor Watch

This half-day seminar takes you under the hood for a range of PC processor designs, providing an inside look at microarchitectures, bus and cache architectures, and performance for the most important PC processors. Youíll get an insightful analysis of Intelís Pentium 4, Pentium III, and Celeron; AMDís Athlon (including Palomino) and Duron; VIAís Cyrix III; Motorolaís PowerPC G4; Transmetaís Crusoe. Each of these processors is evaluated on how it handles superscalar instruction execution, including speculative and out-of-order execution.

- Afternoon Seminar:

Information Appliances: Technology and Architectures

presented by Steve Leibson, Vice President and Chief Analyst at Cahners MicroDesign Resources and program director of the Microprocessor Forum and Embedded Processor Forum.

Many different information appliances are now emerging to enable access to digital media without the complexity of a PC. Information appliances have the potential to further improve the user experience by providing devices optimized for specific functions, and which can be located where they are most naturally used. This seminar will explore the motivations behind information appliances and the reasons why they may succeed--or fail--in competition with PCs. Examples of emerging information appliances--including TV set-top boxes, Web terminals, screen phones, handheld computers, digital cameras, image viewers, and digital music players--will be presented, with block diagrams and evaluations of their technical and market challenges. The seminar will also survey key enabling technologies for information appliances, including microprocessors, system logic, memory, mass storage, displays, batteries, peripheral interfaces, and wireless communications.

- Dinner Presentation:

Next-Generation Lithography for Manufacturing Microprocessors

presented by Chuck Gwyn, Program Director, EUV LLC

Working at the very boundary between theoretical physics and practical engineering, scientists at the Virtual National Laboratory appear to have jumped over many of the obstacles standing in the path of extreme-ultraviolet (EUV) radiationís becoming the industryís next choice for next-generation lithography. How will the extreme imaging technology developed for "Star Wars" be applied to the fabrication of extremely small microprocessors? Youíll find out in this dinner presentation by Chuck Gwyn, Program Director at the EUV LLC industry consortium.

Chuck Gwyn is Program Director at EUV LLC, a limited liability company established in 1997 by Intel, along with AMD and Motorola, to sponsor EUV lithography development and commercialization. Working with scientists at Lawrence Livermore, Sandia, and Lawrence Berkeley National Laboratories--collectively called the Virtual National Laboratory--the EUV lithography effort is funded entirely by the private sector under a $250 million cooperative R&D agreement between the U.S. Government and EUV LLC.

Join your colleagues and the industry's leaders, March 15, 2001.

Select from two half-day seminars and dinner presentation...and get an edge on competition with an insider's preview of rapidly evolving technologies.

Advance Registration Required. See our website for more information. http://www.mdronline.com/march15/