Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Steve Leibson, Kevin Krewell, Peter Glaskowsky, Markus Levy, and Max Baron.

In This Issue:

• Editorial: Back to the Future
• Intel Mobilizes at IDF
• Intel Undercuts HyperTransport
• Java to Go: Part 3
• Embedded Tidbits

Subscribers to the Microprocessor Report will find the following departments updated:

- Chart Watch: Low-Power Processors

(Subscriber Link: http://www.mdronline.com/mpr/cw/cw_mob.html )

- Patent Watch

(Subscriber Link: http://www.mdronline.com/mpr/h/2001/0326/1513pw.html )

- Literature Watch

(Subscriber Link: http://www.mdronline.com/mpr/h/2001/0326/1513lw.html )

- Resources

(Subscriber Link: http://www.mdronline.com/mpr/h/2001/0326/1513res.html )

Editorial: Back to the Future
By Steve Leibson

Now that the dotcom bubble has burst, it seems that some sanity may be returning to our industry--at least for some people. Two speakers at the recent Internet Appliance Workshop, held in San Jose, provided a marked contrast in attitudes, reflecting pre- and post-bubble thinking. Dennis Tsu, director of Managed Appliances and Services at Cisco Systems, delivered a keynote at the workshop that seemed to reflect the go-go thinking that prevailed before the bubble burst. As a manager at Cisco, Tsu focuses on what Cisco's customers say they want. These customers tend to be service providers that are looking to harness as many revenue streams, or annuities, as they can. Consequently, these providers want to offer "managed" services. Another way of looking at managed services is by posing the question Tsu raised shortly after describing what his customers want: "How do we lock our customers in?" he asked. It seems to me that this attitude has become eerily omnipresent since the dotcom balloon went up.

Tsu's question brought back many memories for me. It's the same question that the EDA tool providers (Daisy, Mentor, and Cadnetix) asked in the early 1980s. It's also the same question minicomputer vendors such as Digital Equipment Corp., Prime, and Data General asked in the 1970s and the mainframe vendors asked in the 1960s. To maximize revenues and profits, these design-tool and computer companies sought ways of providing proprietary products and services that locked customers into one vendor's family of offerings. Using history as our guide, we in the electronics industry should by now be far past asking this sort of question. Customers recognize that being locked in is a losing game for them. It's not that I don't want to see vendors maximize their income. Far from it. However, I do want vendors to learn from past mistakes. That should be lesson number one from the burst bubble.

Bob Ferrari, chief strategy officer at Merinta, also delivered a speech at the Internet Appliance Workshop--one that was filled with the lessons of history. Recent history. According to Ferrari, here's what we learned about internet appliances last year:

* Product cost matters.
* Subsidy is a dirty word.
* Business models need to be realistic.
* Your audience may or may not have a PC.
* Users don't want long-term commitments.
* Internet appliances enhance PCs--they don't replace them.

>From my perspective, Ferrari's position appears to have a lot more sanity in it than Tsu's. We know that customers don't want to be locked in unless they receive truly compelling value for the privilege of being "managed." The rapid and tremendous success of DBS satellites is a case in point. Customers are effectively locked into their DBS provider, because only one satellite up there will feed the dish they buy at the local store. However, customers don't perceive this as an artificial lock, because most recognize that it's not easy to loft satellites into geostationary orbits.

Now imagine information appliances that work with only certain Web sites and not with others. (Yes, there are some.) I submit that we're already past the time when vendors can offer such limited wares, because other vendors, with more enlightened approaches to development and marketing, will steamroller the overly greedy purveyors of limited customer choice.

Ultimately, the market decides. If your offering is so compelling that customers will allow themselves to be locked into a relationship with you, then you are truly lucky. But before you decide that your product or service resides in that golden, protected niche that gives you a license to steal, you'd better take a good look around. Many such golden niches aren't nearly as well protected as you might think. Just ask the ghosts of Daisy, Cadnetix, Digital Equipment Corp., Prime, and Data General
.- Steve Leibson

Intel Mobilizes at IDF
Spring '01 Intel Developer Forum Reveals Road to "Banias"
By Kevin Krewell {3/26/01-02}

At the spring IDF, Intel revealed additional details of its mobile roadmap through 2003, and we learned the code-name for a critical future mobile processor-Banias. Intel is pressing forward with a variety of mobile plans that look rather fractured at present. Intel offers three "flavors" of Mobile Pentium III and mobile Celeron processors: standard mobile voltage, low voltage, and ultralow voltage. Each voltage level imposes frequency limits and offers a unique thermal design envelope. The SpeedStep voltages for Intel's Mobile Pentium III processors are 1.6V/1.35V (maximum performance/battery optimized) for standard processors; 1.35V/1.1V for low-voltage processors; and 1.1V/0.975V for ultralow-voltage processors. Intel needs to put together a better framework to explain to users the various trade-offs among voltage, frequency, higher maximum power, thermal design envelopes, and battery life.

Intel did take the opportunity at IDF to introduce a new Low Voltage (LV) Mobile Pentium III processor (featuring Intel SpeedStep technology) at 700MHz, claiming it is "the fastest mobile processor for mini-notebooks." In "maximum performance mode" the processor runs at 700MHz and operates at 1.35V. In "battery optimized mode," both clock frequency and voltage are lowered, and the processor runs at 500MHz at 1.1V. The Low Voltage Mobile Pentium III processor at 700MHz, in ball-grid-array (BGA) packaging, is priced at $316 in 1,000-unit quantities. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0326/151302.html )

Intel Undercuts HyperTransport
By Peter N. Glaskowsky {3/26/01-03}

At the Intel Developer Forum (IDF) this month, Louis Burns, general manager of Intel's Desktop Products Group, announced that Intel plans to develop third-generation I/O (3GIO) technology to replace the PCI bus in desktop PCs. The announcement appears calculated to undercut recent announcements of vendor support for AMD's HyperTransport, which is also meant as a backplane interface for future desktop and server systems.

Burns said that HyperTransport lacks "the scalability, the flexibility, the true performance characteristics to become an industry-standard I/O architecture for the next ten years." This statement was not supported by any further explanation, however, and amounts to no more than an attempt to disseminate FUD (fear, uncertainty, and doubt).

According to Burns, the 3GIO effort will define a flexible point-to-point serial interface that will support copper and optical physical interfaces, provide some scaling through multiple connections between end points, and offer scalability beyond 10GHz signaling rates. A draft of the 3GIO specification will be made available at the next IDF in August. Although Burns claimed that Intel is soliciting input from PC OEMs and other vendors, itís clear that Intel has already decided on the most important features of 3GIO; only minor technical issues can be resolved during the next five months.

If Intel hopes to get any support for 3GIO, it must immediately explain why existing interfaces, such as HyperTransport and RapidI/O, are inadequate or inappropriate for the PC market. Intel must also lay out its reasons for preferring serial interfaces, despite the inherently better price/performance ratio of parallel local interconnects. The next IDF, though only five months away, is too far in the future for the industry to wait for these explanations. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0326/151303.html )

Java to Go: Part 3
Chicory Systems' Java Accelerator Pours a HotShot
By Markus Levy {3/26/01-03}

In the first and second parts of ("Java to Go: Part 1," MPR 2/12/01-01 and "Java to Go: Part 2," MPR 3/05/01-02) popped the lid off three hardware Java accelerators targeted at the embedded market, in particular for wireless and portable applications. Specifically, we examined ARM's Jazelle, Nazomi's JSTAR, and inSilicon's JVXtreme. The approaches from ARM and Nazomi translate Java bytecodes on the fly into the native binary of the host CPU. At the other extreme, inSilicon's accelerator operates as a coprocessor and directly executes a portion of the Java bytecodes. Chicory Systems' HotShot, which we examine in Part 3, implements an entirely different approach and functions as a hardware-based just-in-time compiler (JIT). Fundamentally, HotShot takes the software JIT and transforms it into a silicon implementation. Besides serving as a Java accelerator, a HotShot module can also preprocess other forms of instructions or data to a format that can be processed by a host processor. Beyond the Java module, Chicory's Wireless Media Accelerator will accelerate basic decompression algorithms and is applicable for other compressed media formats.

The general flow of instructions or data through the HotShot engine is fairly straightforward, but the real complexities of this architecture appear in the optimization phase. Aside from instruction folding, the other hardware-based Java accelerators do not perform code optimizations. On the other hand, HotShot can perform code optimizations at the "big picture" level, similar to the performance of software-based JITs. In other words, the optimization hardware continually analyzes the code being translated over a long stream of instructions. For optimizations, HotShot uses adaptive register assignment algorithms based on heuristics; special accumulation techniques to identify related operations that may be combined and performed with a single instruction; and branch-following techniques to identify merge points or to translate down both sides of branches.

HotShot generates code at the rate of one native instruction per cycle, but it does this in blocks that generally correspond to a Java method or part of a method. To minimize the delay associated with redundant bytecode translations, Chicory's HotShot includes a translation cache. The generated code is stored in the translation cache and associated memory regions for future references; the hardware maintains the cache directory and uses a pseudo-least-recently-used (LRU) replacement algorithm.

The interesting question is whether HotShot is a suitable replacement for a software-based JIT: in other words, is it worth the extra silicon, the extra effort for design integration, or the licensing fees? And at the system level, does it significantly help to reduce the energy consumed by a host CPU performing a software-based JIT? (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0326/151304.html )

Embedded Tidbits
By Max Baron

DSP Connectivity Solution from eDevice

On March 6, eDevice (www.eDevice.com) announced SmartStack for Ethernet. According to the announcement, OEMs can now integrate the SmartStack for Ethernet solution into any piece of equipment, converting it into a standalone client that can be connected to any Ethernet local area network (LAN).

SmartStack for Ethernet is claimed to be the only software solution currently on the market that combines both the Media Access Control (MAC) layer (the standard functions needed to connect to a LAN) and the Internet protocols on a single, off-the-shelf DSP. It is said to be a single-chip solution that allows OEMs to integrate into their equipment inexpensive, small-footprint solutions for LAN-ready Internet connectivity. SmartStack for Ethernet targets low-cost, Light Internet devices accessing the Internet in LAN-based environments like offices, medical facilities, shop floors, educational institutions, "smart" buildings, and homes equipped with broadband access. According to the company, it enables direct connectivity without the need for a PC or special ISP and provides Internet functionality (email, FTP, and Web server).

SmartStack for Ethernet is an embedded software solution that executes the MAC layer and the Internet protocols at the same time on a single DSP without using extra gateways or customer code. The system is flexible and the protocols are not proprietary. Developers can integrate SmartStack into their own hardware solution or purchase a turnkey chip set.

LSI Logic Releases 600-MIPS, Low-Cost DSP

LSI Logic Corporation announced on March 6 the introduction of the LSI403Z to its ZSP family of digital-signal processor standard products. Based on LSI Logic's ZSP400 core, the LSI403Z extends LSI Logic's standard product portfolio and is targeted for use in small office/home office (SOHO) and residential gateway applications. These applications deploy and manage high-speed Internet access, Web-based call centers, and other functions that require technology support for high-quality voice and data service. According to LSI, the LSI403Z provides performance and code density to enable designers of digital subscriber line (DSL) and broadband wireless systems to build integrated access devices that provide up to 12 voice channels for increasingly complex system requirements. The company says the low-cost LSI403Z offers performance at pennies per million instructions per second (mips).

The LSI403Z is housed in a 208-pin PQFP package and operates at 150MHz for a maximum throughput of 600 mips. This is achieved via a four-way superscalar engine with four execution units, two multiply accumulate units (MACs), and two arithmetic logic units (ALUs). The LSI403Z can execute two multiply accumulate operations in a single clock cycle while consuming only 2mW/mips (typical) of power. In addition, it supports single-cycle add-compare-select, bit-manipulation, and 32-bit arithmetic and logic operations. The LSI403Z is available now, priced at $8.86 in volume shipments of 50K.

Iomega Increases PocketZip to 100MB

Iomega Corporation announced on March 8 the Iomega PocketZip 100MB drive for handheld consumer electronics devices. Calling it a new low-cost portable storage standard for a new generation of digital audio, video, and imaging devices, Iomega says that the PocketZip 100MB drive leverages the company's PocketZip technology and offers two and a half times the storage capacity of its previous 40MB.

According to Iomega, the new PocketZip 100MB disks will retail for as little as $10 each, much less than 64MB solid-state memory cards, which are priced at about $69. The PocketZip 100MB drive thus lowers the cost of removable storage to as little as ten cents per megabyte, and the company expects it to be the catalyst for a new generation of portable devices from Iomega and its OEM partners.

Sony, IBM, and Toshiba Go for Terraflops

Sony Computer Entertainment Inc. (SCEI), IBM Corporation, and Toshiba Corporation announced on March 12 plans to research and develop an advanced chip architecture for a new wave of devices in the emerging broadband era.

Combining SCEI's experience in the computer entertainment world, IBM's computer and semiconductor technologies, and Toshiba's capabilities in system large-scale integration (LSI), especially for consumer applications, the companies will collectively invest more than $400 million during the next five years to design a "supercomputer-on-a-chip." Under the agreement, the three companies will establish a joint development center within an IBM facility in Austin, Texas. At its peak, the center will be staffed with approximately 300 computer architects and chip designers dedicated to the development project.

Code-named "Cell," the new microchips will employ advanced research technologies and chip-making techniques, including copper wires, silicon-on-insulator (SOI) transistors, and low-k dielectric insulation, with features smaller than 0.10-micron--1,000 times thinner than a human hair. According to the partners, the result will be consumer devices that are more powerful than IBM's Deep Blue supercomputer, operate at low power, and access the broadband Internet at ultrahigh speeds. Cell will be designed to deliver "teraflops" of processing power.