Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Cary D. Snyder, Kevin Krewell, Katherine Bowen, and Max Baron.

In This Issue:

• Microsoft's TabletPC Gains Support
• VIA Unveils C3 at Cebit
• Stretching Silicon to the Max
• Smart Home Networks Heading for Mass Market
• Embedded Tidbits
• Special Promotion
• Embedded Processor Forum 2001

Microsoft's TablePC Gains Support
By Kevin Krewell {04/16/01-01}

At this year's WinHEC (Windows Hardware Engineering Conference), one of the top stories, and the one most misreported, was the TabletPC platform initiative from Microsoft. Bill Gates demonstrated the TabletPC concept model, which has been in development for more than a year, at the opening keynote address for WinHEC. A prototype TabletPC was first demonstrated at last fall's Comdex, using a Transmeta Crusoe processor. The TabletPC is not an information appliance; it is more correctly considered a new form of notebook PC.

Hardware partners announced at WinHEC included Acer, Compaq, Fujitsu, Sony, and Toshiba. Noticeably absent from the initial wave of OEM partner announcements were a number of other important notebook OEMs (Dell, HP, IBM, and NEC) and key Taiwanese notebook suppliers Quanta and FIC. Microsoft's processor partners include both Intel and Transmeta but at present do not include AMD and VIA. Transmeta got a jump on media coverage by issuing a press release before the keynote, leading a number of news organizations to misreport the story as if only Microsoft and Transmeta were working together on TabletPC.

The version of WindowsXP Microsoft plans to offer is the Professional edition, which is normally intended for business users rather than consumers. Although Microsoft's OEM partners did not announce prices, when the TabletPC ships in 2002, its price should be in line with those of ultralight notebooks having similar processor, memory, hard drive, and option configurations. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mpronline.com/mpr/h/2001/0416/151601.html)

VIA Unveils C3 at Cebit
By Kevin Krewell {04/16/01-02}

It sometimes is easy to forget that VIA is in the x86 processor business and not just the PC chip-set business. Although VIA's processor volumes were far below the radar for 2000, it plans to have an impact in 2001. The latest value processor contender is the VIA C3, which is based on the Cyrix III (see MPR 06/26/00-03, "Cyrix III is Dead, Long Live Cyrix III"), introduced last year. The Centaur division of VIA added a full-speed 64K exclusive L2 cache and migrated the design to TSMC's 0.15-micron process. This latest processor keeps VIA on the roadmap presented at Microprocessor Forum 2000 (see MPR 10/23/00-01, "VIA Still Bullish on Centaur") by Glenn Henry, Centaur's president. Centaur is VIA's processor design division, purchased in 1999 from IDT. The C3 (shown in Figure 1) was previously know as the Samuel2 or the C5B, depending on whether you were talking to VIA or Centaur. The C3 is available now at 733MHz. The 1,000-piece list price is $54. An 800MHz version is also expected shortly. See the VIA Web site at http://www.VIA.com.tw for more information. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mpronline.com/mpr/h/2001/0416/151602.html )

Stretching Silicon to the Max
A Deep Analysis of Xtensa's Extensible Performance
By Cary D. Snyder {04/09/01-01}

The topic of configurable processor cores will usually arise in the course of selecting an optimal processor architecture. The selection process is eased by analyzing the way power consumption and cost relate to the number of clock cycles at the lowest frequency necessary to perform a group of tasks. In-depth analysis can lead to combining a general-purpose processor with task-oriented processors that include DSP functions in RISC-type processors.

Two types of cores are emerging to fill this need: fixed-function RISC processors that contain DSP extensions and configurable-at-build RISC processors that include fully customizable instructions and coprocessor hardware.

Tensilica's Xtensa core is one new breed of embedded processor-configurable at build from a custom description of hardware and instructions. Xtensa uses a Verilog-type process called the Tensilica Instruction Extension (TIE) Language. By uniformly applying meaningful baseline performance parameters across a wide range of devices and performance measurement methods, we can establish credible analysis processes for evaluating these types of products. The EDN Embedded Microprocessor Benchmark Consortium (EEMBC) and its certification are major parts of this evaluation process. MDR looks to EEMBC's benchmark suites to provide solid technical data and a means of fully disclosing detailed configuration information. This article looks at the complex analysis process needed to evaluate these new processor types by examining newly released EEMBC benchmark data from embedded processors with custom-processor extensions and DSP coprocessors. The most important aspect of this analysis is its ability to help design teams understand the true cost of achieving performance requirements and the way these requirements relate to code and silicon size, power dissipation, and cost. Comparing simulation and real-silicon results may reveal some issues; however, it is easy to extract essential information that is useful to the system design team.

Tensilica focused on creating three individual cores for three of the five EEMBC benchmark suites: consumer, networking, and telecommunications. Making business sense out of IP cores carrying per-chip royalties isn't a road to riches paved in gold, however. Design teams must consider a number of issues when looking at configurable embedded-processor cores. Paramount are design process and ease of use. Carefully evaluating any IP core provider is more important now than in the past. Configurable embedded processors are developing into an interesting offering-and they are certainly capable of stretching silicon to the max. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0409/151501.html )

Smart Home Networks Heading for Mass Market
By Katherine Bowen {04/09/01-02}

Editor's note: Today, more than ever before, successful microprocessor and DSP innovations are linked to applications in systems; these, in turn, depend on forecasts of market demand and on the status of the electronics business. In most companies, engineering, marketing, and business-development executives expect to review both technical and business aspects of new ideas. Startups must provide the same information to their investors. Microprocessor Report has recently increased its coverage of embedded computing to include discussion from the point of view of system applications. As an added service to our subscribers, Microprocessor Report will begin to publish a monthly Electronic Business Analyst's Corner. In it, our subscribers will find useful information about technology and system business opportunities, market shares, and forecasts. We hope that these may help stimulate innovative ideas and optimize the competitive positions of existing products. Created by the business side of our organization, In-Stat (and others), these analyses will represent the most updated projections in areas of interest to our subscribers. Please give us your feedback at mbaron@mdr.cahners.com. --Max Baron

Although home automation emerged three decades ago, such systems have yet to penetrate the mass market or become a realistic option for the average homeowner. Recent developments are making the smart home more affordable and accessible, however, while offering an increasing number of desirable capabilities. The market is on the verge of rapid growth, with traditional home automation system vendors nearly doubling the number of new installations during the past year.

Ubiquitous Internet access, plus increasing interest in home networks, is creating a new market segment that encompasses traditional home automation systems. The smart home network, essentially a home network of intelligent devices capable of linking to the WAN and being remotely accessed and controlled through the Internet, telephone, or WAP cellphone, is transforming home automation. Smart home networks are expected to drive sales of controllers and nodes serving this market from $180 million in 2000 to $1.7 billion in 2005. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mpronline.com/mpr/h/2001/0409/151502.html )

Katherine Bowen is a senior analyst with Cahners In-Stat Group. She can be reached at kbowen@instat.com.

Embedded Tidbits
By Kevin Krewell

IBM Joins EUV Consortium

IBM announced on March 12, 2001, that it would join the extreme UV limited partnership (EUV LLC). It joins semiconductor manufacturers Advanced Micro Devices, Infineon, Intel, Micron Technologies, and Motorola in supporting the research. The EUV program (see MPR 6/19/00-01, "Extreme Lithography") plans to develop and commercialize lithography equipment that uses soft X-ray radiation. IBM views its participation in EUV as complementary to its plans to develop direct electron-beam lithography. It plans to use electron beam and EUV in a "mix and match" process.

Intel Moves Celeron to 850MHz

Much like the manipulation of pawns in a chess game, AMD and Intel keep pushing forward their respective value-processor product line--one step at a time. Intel's latest move is to 850MHz for the Celeron line of value processors; AMD moved its Duron processor to 900MHz earlier this year. The latest speed grade of Celeron began shipping on April 9, 2001. In 1,000-unit quantities, the Intel Celeron processor at 850MHz costs $138.

Special Promotion

MDR Analysts Target Information Appliances and Embedded Processors in Convergence University Seminars

Join Steve Leibson and Markus Levy on Friday, May 30 for a special program of four 90-minute seminars to be held as part of this year's ConVergence University - where an international audience of development engineers will join leading semiconductor companies and development tools suppliers for three days of intensive hands-on training in the largest event of this kind in the embedded industry.

For more details on the seminars to be presented by Steve Leibson and Markus Levy, please visit the MDR web site at www.mdronline.com/cu_seminars/

To register on line, please visit the ConVergence University web site at http://www.ConVergenceU.com.

Embedded Processor Forum 2001

Cahners MicroDesign Resources Presents
Embedded Processor Forum 2001

The conference for embedded technology

Don't miss more than 20 first disclosures of new chips and cores plus four full-day seminars by the industry's most respected analysts. And a unique opportunity to gather with the brightest, most innovative processor designers on the planet. That's Embedded Processor Forum - the embedded industry's most important week of the year

And new this year! MDR Network Processor Forum

A full day of panels and sessions devoted to new network processors and their silicon technologies, including control and data-plane processors, switched-fabric chips, DSPs for communications, and more.

The latest chips, the freshest insights, the sharpest analysis

Whether you're designing networks, information appliances, or computer games . . for low power, high performance, or DSP technology . . . Embedded Processor Forum gives you the in-depth technical information you need to make a winning embedded design decision.

June 11 - 15, 2001
Fairmont Hotel
San Jose, California

Register on line at http://www.MDRonline.com/epf or call 1.800.527.0288 or 1.408.328.3900