Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Steve Leibson, Max Baron, Markus Levy, Peter N. Glaskowsky, and Cary D. Snyder.

In This Issue:

• Editorial: Mortals, Muggles, and Information Appliances
• MSA 2500
• Finding More Open IP
• Processors Vie for Home Gateways
• National Buys Into TriMedia
• Toshiba Brings Emotion to Market
• Embedded Processor Forum 2001

Mortals, Muggles, and Information Appliances
By Steve Leibson

In last month's editorial, I harangued information appliance companies with insane business models that focus more on revenue streams than on customer satisfaction—short-term thinking. This month, I'd like to look at a closely related aspect of companies that don't take customers seriously.

In the latest version of my Information Appliances seminar, I define an information appliance as "a consumer product that consumes information (bits) from a variety of sources (including the Internet) to produce a useful result." That's the ideal definition. In my seminar, however, I go further, defining today's Internet appliances as "expensive, complex products, available only from Internet sites or computer stores, that require an MSEE or better for successful installation." You can get a more complete education on this concept by reading the book The Inmates Are Running the Asylum: Why High Tech Products Drive Us Crazy and How to Restore the Sanity by Alan Cooper and Paul Saffo.

Why are the inmates (the technology cognoscenti) running the asylum? Because they design the products. This situation is a badly overgrown version of the way we designed products at HP during the neolithic era of electronics (the 1970s). Back then, we called the approach "next-bench" marketing. Today, you'd call it "nerd marketing."

The key philosophy behind this approach is to take your newly minted idea for a product or feature, pop up from your chair, hang your arms over the cube wall, and ask the person next to you if your idea has merit. If that person answers yes, then you've obviously got a winner. If you get a negative response, then you probably didn't explain it very well, so you try the person on the other side of your cube. Next-bench marketing may be fine for oscilloscopes, voltmeters, and similar items used by engineers and other geeks, but it doesn't replace good market research when designing consumer products like information appliances.

As in the old TV sitcom Bewitched or in J.K. Rowling's immensely popular Harry Potter books, the world is mostly populated by people not in the know. These unenlightened ones are called mortals in the TV show and muggles in the books. As in these fictional worlds, we wizards, witches, and warlocks (the technology elite) coexist with technological mortals and muggles, and we have at least a slight disdain—if not outright enmity—for the unenlightened.

Many in Silicon Valley have a blanket reference for these people. Depending on their age, these unenlightened wizards refer to technology mortals as mothers or grandmothers. (Clearly, the Valley contains a strong sentiment that all our mothers and grandmothers are or were technological nincompoops. It makes you wonder how we wizards got so smart.) In any case, the vast majority of people in our target markets do not have advanced engineering degrees, and they do not share our technological knowledge or frame of reference, but they are the people who, we hope, will buy our shiny new information products in great numbers. They won't buy, however, unless we design products they can use.

If you want to design products that mortals and muggles can use (and will therefore want to buy), there are some concrete things you can do. First, swear off nerd marketing. Next, if you want to sell to a particular audience, consider obtaining the design services of someone familiar with that audience. The job title Cooper and Saffo recommend for this task in their book is "interaction designer"; some industrial design companies can also provide this expertise.

Another approach involves explaining your ideas to a sample of your target audience by running focus groups or usability labs. Unless your organization is blessed with an experienced market researcher or an in-house usability lab, you have no one qualified to do this work. Hire someone who knows how to run such groups and labs and you will get value for money spent. Otherwise, just toss the money out the window, wave your wand, cast a spell, or ask the person in the cube next to yours. Same effect.

MSA 2500
A First Look at Adaptive Silicon's Programmable Multi-Scale Architecture
By Max Baron {4/30/01-01}

Microprocessor Report takes a first look at a new, reprogrammable ASIC core technology aimed at producing ASICs and application-specific standard products (ASSP) that can be differentiated and upgraded and may reduce risk in new designs. Offered by Adaptive Silicon Inc. (ASi), an intellectual property (IP) provider, the new technology comes in the form of programmable soft cores that can be embedded in ASICs. Programming of these cores resides in on-chip RAM, which must be initialized at boot time in a manner similar to that of FPGAs but may also be changed at runtime. Dubbed MSA 2500, with MSA standing for Multi-Scale Architecture, the new cores are not yet completely characterized. Datasheets are not publicly available, nor are clear descriptions of core features and benefits.

For our first look at this technology, we have assembled a functional description of the cores based on our deduction of internals and on partial answers received from ASi. The company is still in process of ensuring that its collection of patents reflects its intellectual property. Programmable cores implemented in ASIC technology have both drawbacks and advantages: frequency-wise, in an apples-to-oranges comparison, ASi's new cores seem to be at a disadvantage when compared with recent FPGA announcements. Cost-wise, they more than make up for such disadvantage by being ASIC cores at ASIC-volume prices. They also support parallel structures that may compensate for their slower speed. We conclude with a quick look at ASi’s new programming challenge—static and dynamic. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0430/151801.html)

Finding More Open IP
OpenMORE Pushes Ease of Use and Reuse
By Cary D. Snyder {4/30/01-03}

Use of intellectual property (IP) cores in embedded-processor design space is increasing in many ways—designing for reuse from the very beginning of an IP module's design or whenever a module is updated. The number of microprocessor IP cores and providers seems to grow daily. Virtually every company has an "IP portfolio." At the same time, use of hard, soft, and configurable cores for system-on-a-chip (SoC) designs is becoming more common—with new and improved design processes and design flows. Newer silicon geometries enable lower costs per gate that encourage larger die sizes; however, this size increase also increases design costs, to the point that the cost of a die mask set exceeds $1 million. Design time of the larger devices can increase dramatically unless strict measures are taken to employ and encourage IP reuse.

This article presents an overview of the current IP market, with a focus on minimizing or reducing the risk with using IP cores. The risk of using IP processor cores without fully proven software components can be loss the of a design team’s most precious resource—time.

A clear case for quality IP has emerged. The quality of the IP itself, or capability of the integration team doesn't drive quality: it is largely defined by how easy it is to use and the amount of time it takes to get all IP blocks functioning together as a system. Time becomes the factor driving IP use.

Call it what you like—cycles of learning, design team experience and resources—time is what it all comes down to. The OpenMORE (Open "Measure Of Reuse Excellence") assessment program establishes a open IP usability index that is similar to those developed within large companies. These documented reusability standards can be used as a measure of quality, and with experience, it can be used as a bases to predict how well functional modules or IP components come together and perform as a system—meeting engineering schedules with reliable products. At the same time, the OpenMORE may be self-serving for those EDA companies that introduced it—they are setting themselves up as judges of quality! (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0430/151803.html)

Processors Vie for Home Gateways
By Markus Levy {5/7/01-01}

There's no argument that Motorola has done a tremendous job of penetrating the networking application space with its PowerQUICC family of processors. Cahners In-Stat Group statistics indicate that the company has 80% of the market share for communications processors. It is the incumbent vendor, with many OEMs, and it continues to proliferate the PowerQUICC product family, although other semiconductor vendors are working feverishly to capture market share.

This observation is especially true in the rapidly growing home connectivity arena and, more broadly, in applications classified as customer premises equipment (CPE). In fact, right on top of Motorola's recent MPC862 family, MPC857T, and MPC850DSL PowerQUICC announcements, IDT announced its RC32355. This is just part of the story, as indicated by devices from Alchemy, Broadcom, Cirrus Logic, Hitachi, IBM, Infineon, Ishoni, Samsung, TI, Virata, and more (see MPR 12/18/00-04, "ColdFire Device Supports Telecom").

Motorola's 862 family and 857T PowerQUICC products fill a PowerQUICC family gap: products to handle simultaneous Fast Ethernet and UTOPIA. In addition to the Fast Ethernet and UTOPIA ports, the new devices support UTOPIA II Multi-PHY, UTOPIA slave, AAL2, VBR, and port-to-port switching. Motorola also announced its MPC850DSL, another PowerQUICC device, but one focused on the low end of the DSL CPE market.

Recently, IDT has become more "networking"-serious with its introduction of the RC32355, a device that includes ATM, Ethernet, USB, and telephony interfaces, along with the 32-bit RISCore 32300 core (MIPS architecture). Like the MPC857T, the RC32355 targets CPE and includes a Fast Ethernet controller and an associated Ethernet media access controller (MAC) that supports up to four MAC addresses. The RC32355 can also perform simultaneous Fast Ethernet (MII) and parallel ATM. The RC32355 includes a time-division multiplexer (TDM) bus interface, used to directly access external devices like telephone CODECs and audio ADCs and DACs. The RC32355 includes a 16-channel direct memory access (DMA) engine; the multiple channels allow the ports to have dedicated transmit and receive channels. Other features of the DMA include an integrated virtual channel cache, used to store header information for data packets. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0507/151901.html)

National Buys Into TriMedia
By Peter N. Glaskowsky {4/30/01-04}

National Semiconductor has established a strategic relationship with TriMedia Technologies, a Philips spinoff, that gives National a license to the TriMedia core and a "substantial" equity stake in the smaller company. National will use the TriMedia core in future members of the Geode family being designed for use in information appliances. Terms of the deal were not disclosed.

The VLIW TriMedia core will be used as an on-chip coprocessor to Geode's x86 processor to accelerate multimedia processing. TriMedia already offers an extensive library of multimedia software for its core. The Geode x86 core, a Pentium-class design currently available at speeds up to 333MHz, is not particularly efficient at multimedia processing. For example, current Geode parts cannot perform software DVD decoding. Licensing TriMedia is almost certainly simpler, faster, and less expensive for National than redesigning the Geode core to keep up with modern applications.

National has not released details of the upcoming Geode/TriMedia products but expects to ship first samples of a Geode processor with an integrated TriMedia core by 1H03. For more information, visit www.national.com. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0430/151804.html)

Toshiba Brings Emotion to Market
By Peter N. Glaskowsky {4/23/01-01}

Toshiba America Electronic Components (TAEC) has announced plans to spin off the San Jose group that developed the Emotion Engine processor core for Sony's PlayStation 2 into a new company called ArTile Microsystems. ArTile will offer the 64-bit MIPS-based core, without the Emotion Engine's associated vector-processor units, as the TX79. The TX79 is the centerpiece of ArTile's plans to develop systems-on-a-chip with customers in markets as diverse as networking and digital TV.

TAEC has high hopes for the new company, which will be headed by Toshiba veteran Tomohisa Shigematsu. ArTile's revenue target is $250 million in 2004—a hefty sum for a new company with a new core—and its plans include an eventual IPO, which should help ArTile attract and retain engineers in the competitive Silicon Valley employment market.

ArTile will build on Toshiba's experience with MIPS-based microprocessors and integrated peripherals, using what ArTile calls a "tile-based design methodology" (hence the name of the new company). ArTile may also benefit from access to Toshiba's sales channels. ArTile is now sampling a silicon implementation of the TX79 and expects production to begin in the second half of the year. Predictably, ArTile will use Toshiba's foundry services, although it has the option of using other foundries. The TX79 core will not be offered as licensed IP, avoiding direct competition with IP vendors such as ARM. It may be easier for ArTile to manage all TX79-based designs itself, but this approach may not meet the needs of all customers. If ArTile cannot convince a potential customer that it can implement or license all the elements required for the customer's system-on-a-chip design, the customer will probably go the more flexible IP-licensing route. For more information, contact Jim Smith of ArTile Microsystems at 408.526.2431 or via email: jim@artilemicro.com. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0423/151701.html)

Embedded Processor Forum 2001

Cahners MicroDesign Resources Presents
Embedded Processor Forum 2001
The conference for embedded technology

Don't miss more than 20 first disclosures of new chips and cores plus four full-day seminars by the industry's most respected analysts. And a unique opportunity to gather with the brightest, most innovative processor designers on the planet. That's Embedded Processor Forum—the embedded industry's most important week of the year

And new this year! MDR Network Processor Forum

A full day of panels and sessions devoted to new network processors and their silicon technologies, including control and data-plane processors, switched-fabric chips, DSPs for communications, and more.

The latest chips, the freshest insights, the sharpest analysis

Whether you're designing networks, information appliances, or computer games . . for low power, high performance, or DSP technology . . . Embedded Processor Forum gives you the in-depth technical information you need to make a winning embedded design decision.

Embedded Processor Forum 2001 News Flash

We have more than one surprise planned for you at this year’s Embedded Processor Forum! Here are the latest additions to our program taking place June 11-15 at the San Jose Fairmont:

TriMedia Technologies will mark its first EPF appearance since spinning off from Philips with the unveiling of system prototype silicon and system integration details for its TM32 VLIW core, a 5-issue slot VLIW processor architecture designed for high-performance media processing. Kees Vissers, principal architect at Trimedia and a 20-year veteran of Philips Research, will take us inside the TM32 on the afternoon of the first conference day,

Tuesday, June 12.
How does your swing measure up? Find out at this year’s EPF. At this year’s MDR Embedded Processor Expo, you’ll see a demonstration of the Swing Solutions GVA500 Golf Video Analyzer—the most advanced portable golf training system in the world. We’ll have a look at this intriguing application for embedded processor technology at the close of our afternoon sessions on Tuesday, and on Wednesday night you’ll have the chance to try the GVA500 for yourself at the MDR Embedded Processor Expo. Fore!

Register now while you’re thinking about it!
Complete program details and fast on-line registration are available now at www.mdronline.com/epf, or call us toll-free at 800.527.0288 (408.328.3900 outside North America).