Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Steve Leibson, Kevin Krewell, Peter N. Glaskowsky and Cary Snyder

In This Issue:

• So Long Alpha
• Speedier BookE Encore
• GameCube Focuses on...Gaming
• Tidbits
• Microprocessor Forum 2001

Editorial
So Long Alpha
By Steve Leibson {7/23/01-02}

By now you should know that Compaq has pulled the plug on the Alpha RISC processor. Alpha's wheels have yet to spin down, but the power's definitely switched off. Compaq announced in June that it will curtail Alpha processor development after 2003 and Alpha-based systems development after 2004. The company says it will add two speed upgrades to the existing EV68/21264 processor, finish developing the next architectural enhancement (the EV7/21364), and that's it. Alpha software teams will immediately start to target Itanium, not Alpha. By the year 2004, bye bye Alpha. Also, bye bye MIPS. Compaq currently uses MIPS processors in its NonStop Himalaya servers, which the company got through its Tandem acquisition. Compaq's future servers will be based on Intel's Itanium.

There can be little debate that adopting Itanium is something Compaq must do. Through acquisitions, Compaq has put itself into exactly the same bind that DEC was in a decade ago. Back then, DEC rode the dual horses of the MIPS and proprietary (VAX) processor architectures. DEC let neither win, adopting Alpha instead of either incumbent. By buying DEC and Tandem, Compaq's server groups now ride three horses: Alpha, MIPS, and Pentium Xeon. Now you know which horses Compaq shot. But you should have known it all along. Back in 1996, then editor in chief Linley Gwennap predicted that workstation and server vendors SGI and DEC would ultimately abandon their proprietary RISC designs and jump on the Itanium bandwagon, several years before the wagon got its wheels.

Alpha leaves a significant legacy in the history of microprocessors. It was designed like a racing car: speed first and foremost. Throughout the 1990s, Alpha was the speed leader in integer performance by a wide margin, thanks to its combination of a simple (hence fast) instruction set, dynamic logic, and bleeding-edge circuit design. Circuit wizards in the Alpha dungeon pushed DEC's relatively low-volume manufacturing facility to produce faster parts at a given lithography level than commercial semiconductor vendors could hope to achieve. Only occasionally did competitors catch DEC, when the company was slow to make a process upgrade.

The Alpha processor joins a number of other worthy microprocessors on the historic scrap heap. There's the AMD 29000, a RISC processor originally designed to be a Unix workstation engine, which became a successful embedded processor before fading out. There's Intel's 960 series, with similar design heritage and a similar fate, after bloodily wresting the laser printer market from Motorola's 68000. There's Motorola's innovative 88000 family, which could never crawl out from under the shadow of the 68000 and that possibly put the stake into Data General. Ditto the ill-fated Fairchild Clipper, which inflicted severe collateral damage on Intergraph before Intergraph cast off the demon. Both Data General and Intergraph dumped their essentially proprietary RISC processors for Intel's P6. The list of fine-but-obsolete processors continues to grow.

From a technical standpoint, it seems to me that Itanium, or something like Itanium, has to win the microprocessor wars for high-end servers, because VLIW (or EPIC in the case of Itanium) simply makes more sense than continuing the increasingly difficult battle to augment RISC processors' superscalar capabilities. One of the original advantages of RISC design, reduced transistor count, has long since disappeared with the addition of superscalar operations as a speed enhancer. The additional layering of superscalar bells and whistles increases a processor's IPC rating, but with a quick limit. Shooting for more than four-issue superscalar operation is a dead end.

Conversely, the VLIW approach relegates the search for code parallelism to the compiler, thus allocating one or more compilation processors and relatively abundant compile time to this task, in stark contrast to the relatively few transistors and real-time constraints that superscalar approaches impose. Argue all you want about the elegance of the Itanium architecture, VLIW is just a better approach to instruction-level parallelism than superscalar RISC is. As a high-end RISC race car, Alpha is dying a natural death.

On the business side, Compaq's decision also makes a lot of sense. Compaq is a company built upon, and steeped in, compatibility. The company was founded on the concept of close IBM PC compatibility in a (purportedly) portable form. Taking an industry-incompatible approach to high-end servers seems to be an unfortunate exercise in corporate dissonance. It's good to see Compaq's leadership step up and make a hard decision to end the experiment.

So who remains? Sun and IBM. IBM seems unlikely to wind the entire company around the Itanium pole. Unlike Compaq, IBM prefers to create standards; it doesn't follow them without a strong strategic reason. The company has successfully built systems to its own standards for decades. IBM seems well committed to the PowerPC from one end to the other. Yet if you look at Intel's Web site, you'll find IBM listed as an early Itanium adopter in both the server and workstation categories. The camel's nose is already under IBM's server tent.

I think it will be a very long time before Sun Microsystems accepts an Itanium-clad future. Sun has already set one of the microprocessor standards in the workstation and server market (after chucking the 68000 many years ago). Sun has captured nearly half the server market, so there's little for the company to gain by adopting Itanium today. In fact, now that Compaq has declared a concrete end to Alpha systems, you should expect Sun to quickly try to gain market share by aggressively targeting existing Alpha system customers as likely sites for conversion to SPARC-based servers. After all, if a Compaq server customer knows it must port its software from Alpha, it's just as easy to port to SPARC as to Itanium, and it's probably safer too, because the compilers and associated software-development tools for SPARC are more mature than those available for Itanium. Sun will need to convert to Itanium only when Itanium-based servers and workstations start to consume some of Sun's market share. That won't happen this year.

Speedier BookE Encore
Motorola e500 Eclipses IBM 440 ...for the moment!
By Cary D. Snyder {7/23/01-01}

Motorola’s first PowerPC Book E architecture implementation, the e500 processor core, was officially launched on June 12, 2001, at MDR’s Embedded Processor Forum. The first public disclosure of the e500 core was in Joseph Chang’s presentation in the 32-bit SoC cores session at San Jose’s Fairmont Hotel. The e500 core is based on the PowerPC architecture and is optimized for wide-range use in system-on-a-chip (SoC) applications. The primary design goal in developing the e500 was to find the optimal balance of the core size with IPC (instructions per clock) performance, low power, and real-time OS (RTOS) features. To ensure that it wasn’t just following IBM with a similar Book E PPC core, Motorola pushed its core in several directions at once: process technology, core and interconnect clock speeds, and features to improve real-time computing.

Coming a year and a half behind IBM with its PPC 440 Book E core, Motorola took every opportunity to enhance the Book E architecture for its targeted applications (see MPR 10/25/99-03, "IBM PowerPC 440 Hits 1,000 MIPS"). At the maximum estimated clock speed of 800MHz, Motorola will be able to claim the highest-performance PowerPC core, cranking out 1,800 Dhrystone mips. Motorola is likely to have a higher-performance PPC Book E core than IBM has at the expense of being 50% larger: IBM’s PPC 440 core, at 0.18µm, is in about 4mm² of silicon, and Motorola’s e500 PPC core will debut at 0.13µm in about 6mm² of silicon.

The original agreement on Book E architecture between IBM and Motorola outlined a plan to develop a common architecture that both companies could modify to suit individual requirements. Both cores-the previously released IBM 440 and Motorola’s e500-have a common subset of Book E compliance. Under the new Book E agreements, which include the e500, Motorola can now license e500-based PPC cores to others-a benefit that may be more significant to Motorola than are the technical improvements.

In networking and communications equipment, the PowerPC architecture reigns as king. A good a start for the e500 and Motorola would be a follow-on PPC architecture that is able to maintain a leadership role for PPC ISA. However, like any successful architecture, each succeeding generation must stand on its own-asserting itself as a market leader. Most new technical features in the e500 core do not break new ground; the way the technology is put together as a system and what Motorola can do with the results strengthens Motorola’s semicustom ASIC business. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0716/152901.html).

GameCube Focuses on...Gaming
By Peter N. Glaskowsky {7/23/01-03}

On November 5, into a market that Sony’s PlayStation and PlayStation2 consoles currently dominate, and only three days ahead of Microsoft’s planned Xbox launch, Nintendo will introduce its next-generation GameCube system.

Everything about GameCube is designed to enhance gaming. The optical drive uses 8cm discs that are more portable than full-size DVDs and less prone to unauthorized duplication, owing to antipiracy features Nintendo will not describe. An optional modem and broadband adapter will be used for multiplayer gaming over the Internet and not for Web browsing, per se.

The hardware architecture of GameCube is simpler than that of either PlayStation2 or Xbox. The GameCube motherboard contains just two major ICs plus memory. One of the larger chips is a custom IBM processor code-named Gekko and built around the PowerPC 405 core. Gekko connects to only one other device in GameCube, the ATI/Nintendo "Flipper" system controller and 3D accelerator.

Nintendo has not revealed all the features of Gekko and Flipper, pending a conference for GameCube software developers in August. Microprocessor Report will provide a more detailed description and analysis of these chips when more information becomes available.

Tidbits
By Kevin Krewell {7/23/01-04}

Intel Boosts Celeron to 900MHz

Intel released two new Celeron processors on July 2, 2001—900MHz desktop part and an 850MHz mobile Celeron. The 900MHz desktop Celeron still lags AMD's Duron processor, which is available at 950MHz. The mobile Celeron does match the fastest mobile Duron at 850MHz.

The desktop Celeron at 900MHz is priced at $103 in 1,000-piece quantities. The mobile Celeron at 850MHz is priced at $134. Both parts are available now.

Intel Fills In Pentium 4 Gaps

On July 2, 2001, Intel rolled out two new Pentium 4 speeds—1.6GHz and 1.8GHz. The 1.8GHz speed is Intel's fastest Pentium 4 until the 2.0GHz version ships later in 3Q01.

Despite being the fastest Pentium 4 processors today, the 1.6GHz and 1.8GHz versions can be viewed as "gap fillers" between the 1.5GHz, 1.7GHz, and (soon to ship) 2.0GHz versions. There could be a number of reasons for Intel's adding these speed grades. Filling the gaps allows Intel to offer more price and clock-speed options for Pentium 4 systems. It also allows Intel to raise margins slightly. (Previously, the 1.8GHz part would have shipped as a 1.7GHz processor with a correspondingly lower price.)

In 1,000-unit quantities, the 1.8GHz Pentium 4 is priced at $562. The 1.6GHz version is priced at $294. Intel is also reestablishing higher price points for the fastest Pentium 4 after the very aggressive introduction price ($362) of the 1.7GHz Pentium 4.

Microprocessor Forum 2001

Come Celebrate 30 Years of the Microprocessor at Microprocessor Forum 2001
October 15–19, 2001 at the Fairmont in San Jose!

• HEAR first disclosures of more than 20 new microprocessors.
• LEARN about the latest and most advanced architectural concepts.
• NETWORK with the leaders of the microprocessor revolution and see where they are going next.
• ABSORB penetrating insights from award-winning analysts.

• An incredible line-up of new processor introductions
• Look into the future and predictions for microprocessor design for the 21st century
• 3 days of keynotes and sessions
• 2 days of seminars including 2 half-day seminars on Monday October 15th.
• The 14th Annual Microprocessor Report Awards

Is the microprocessor over-the-hill at 30? Where do we go from here?
Find out what happens next at the 14th Annual Microprocessor Forum

Register on line at www.mdronline.com/mpf or call (480)483.4441 (in Scottsdale, AZ)