Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Markus Levy, Max Baron, Kevin Krewell, Jonah Holmes, and Jeff Bier.

In This Issue:

• Intel/ADI DSP Core Gets a Home
• Transmeta 2Q01 Results Fall Short
• LSI, Ericsson Combine DSP and Reconfigurable Logic
• ST's SkyCore Targets Automotive Multimedia

Intel/ADI DSP Core Gets a Home
Analog Devices Intros First MSA-Based Device
By Markus Levy {7/30/01-01}

The ADSP-21535 is the first member of the Analog Devices Blackfin family, which is based on the architecture jointly developed with Intel. In addition to the MSA core, the 21535 contains a host of memory and peripherals, including 308KB of SRAM, two UARTs, two serial port interface (SPI) ports, a PCI and USB controller, an SDRAM controller, two synchronous serial ports (SPORT), a real-time clock, and three general-purpose timers. ADI is using the 21535 to target video-enabled Internet applications that include video telephones, gaming devices, Web terminals, and smart handheld devices.

The 21535's UARTs, SPI ports, and timers are standard features these days on DSPs and other integrated processors, but the combination of PCI and USB is a unique feature among DSPs. Also unusual in the DSP world, the 21535 includes a memory management unit (MMU) to provide memory protection in conjunction with the core's user and supervisor modes for support of a operating-system kernel.

The two SPORTs are for serial and multiprocessor communications. These are the same ports that ADI has reputably included in its 219x family of devices and are not the "link ports" seen on the SHARC processors in multiprocessor systems. The biggest chunk of memory within the 21535 is 308KB of SRAM that can be configured as SRAM, caches, or a combination of both. The smallest memory block is a 4KB scratchpad RAM that is accessed at the processor core frequency.

The intelligence behind the 21535 is the new DSP architecture from ADI and Intel. The architecture combines a dual-MAC 16-bit fixed-point digital signal processor and the instruction set of a microcontroller. In addition to the MACs, the Data Arithmetic Unit includes two 40-bit ALUs, four 8-bit video ALUs, and a 40-bit barrel shifter. The DSP core contains two data address generators (DAG) to help feed the dual computation units. The DAGs support bit-reversed addressing and circular buffering for DSP algorithms and support loads and stores, autoincrement, autodecrement, and base-plus immediate-offset-addressing modes for microcontroller functions.

Blackfin supports multilength instructions, mixing up to three instructions in parallel, with some limitations. The fully protected MSA pipeline has eight pipeline stages: instruction fetch 1, instruction fetch 2, decode, address, execute 1, execute 2, execute 3, and write-back. Blackfin's instruction format includes a branch-prediction appendix that helps the processor improve branch instruction performance. The default is branch-predicted-not-taken.

The Blackfin DSP is the first DSP with dynamic power management, allowing independent adjustment of both voltage and frequency to minimize the energy consumed by specific tasks. Frequency has 32 control levels; voltage has 8. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0730/153101.html).

Moto Moves ARM to DragonBall MX1
Part 1: A Strategy in Silicon
By Max Baron {7/23/01-01}

Motorola recently announced its first everything-on-a-chip 200MHz DragonBall MX1 (Multimedia Extensions) chip, which uses an ARM core. The announcement was surprising because of the short time that has passed since Motorola acquired an architectural license from ARM. The surprise was made even more interesting by how close MX1 comes to being a true system-on-a-chip for mobile systems-and others.

Enriched with a wealth of peripherals and system services, the DragonBall MX1 was well into its development before the end of 2000, with samples expected before the end of 2001. It is not using the Java extensions (Jazelle) nor the multimedia extensions, both of which are relatively new additions to the ARM architecture. It may not need them. The present DragonBall MX1 is not a result of an ARM architecture enhancement by Motorola, such as we may expect to soon see coming up under its architectural license. It is a tour-de-force in integration that reinforces Motorola's position in mobile electronics. This article is the first in a two-part coverage. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0723/153001.html ).

Editor's Note: Low-power x86 compatible processors and chipsets are finding their way into more embedded applications. Traditional PC-related items appearing in Microprocessor Watch (MPW) are also included in EPW when they relate to the embedded market. —CDS

Transmeta 2Q01 Results Fall Short
By Kevin Krewell {7/30/01-05}

Transmeta has reported sales of $10.5 million dollars for 2Q01, down sharply from the $18.6 million recorded in 1Q01. Transmeta blamed lower ASPs and slowing in the Japanese economy for the shortfall. The company reported a pro forma loss of $17.8 million and an actual net loss of $69.3 for 2Q01. The pro forma results exclude charges taken in the quarter to write off excess inventory ($28.1 million), the purchase of in-process technology from AMD ($13.6 million in stock), amortization of intangible assets, and deferred stock compensation.

Transmeta expects systems with the recently announced TM5800 and TM5500 to ship in October in tandem with the launch of WindowsXP. The company characterized the shipping date for the next-generation VLIW core and the highly integrated Crusoe as late 2002.

LSI, Ericsson Combine DSP and Reconfigurable Logic
By Jonah Holmes and Jeff Bier, BDTI {7/30/01-02}

BAZIL, a new heterogeneous communications processor architecture jointly developed by LSI Logic and Ericsson, was presented in June at the Embedded Processor Forum in San Jose. BAZIL targets communications infrastructure equipment by integrating LSI's "ZSP" DSP core with two ePLCs (reconfigurable logic blocks).

The ZSP core, which LSI Logic obtained through its acquisition of ZSP Corporation in 1999, is a 16-bit fixed-point superscalar DSP that operates on both 16- and 32-bit data types. With four execution unitsótwo MACs and two ALUsóthe ZSP can execute up to four instructions simultaneously. The ZSP core, recently licensed by Broadcom, Conexant, and IBM, has replaced DSP Group's Oak DSP core as the main DSP in LSI's IP portfolio. The two ePLCs, or "Liquid Logic" blocks, are ALU-based programmable logic blocks. In BAZIL, the ZSP runs at 160MHz and the ePLCs run at 40MHz; according to LSI, both clock speeds have been scaled back to match available memory bandwidth.

Subtasks of an application are mapped onto either the ZSP core or an ePLC block according to the complexity and computational demands of the subtask. The ePLC can handle the more computationally demanding functions that are less complex and more repetitive, i.e., tasks that are most amenable to parallelization and that require parallelization to meet application performance requirements. The ZSP core takes care of the less regularly structured and less computationally demanding functions.

LSI licensed the ePLC technology from Adaptive Silicon, neatly rounding out LSI's IP portfolio for communications applications—it now offers reconfigurable logic, DSP cores, general-purpose processor cores, and ASIC capability. This puts LSI in a strong position: it can offer ASIC customers a diverse array of building blocks; moreover, LSI can draw from these elements in its own ASSP designs. LSI has not yet announced plans or pricing for BAZIL-based products, but, if nothing else, BAZIL is a good proof of concept for LSI's integration capabilities—capabilities that will become increasingly important as applications demand solutions that are more highly integrated.

But how effective is the combination of subsystems found in BAZIL? LSI and Ericsson presented FFT benchmark data for the ePLC subsystem, but the data suggests that the ZSP and two ePLCs together would not be as fast on this benchmark as a higher-performance DSP, e.g., TI's forthcoming 600MHz TMS320C64xx. For algorithms that are less well-suited for efficient implementation on a DSP processor, for example, bit-manipulation-intensive algorithms like Reed-Solomon decoding and decryption, the ePLCs will likely provide significant performance gains. Speed, however, was probabl not LSI's only consideration: the ability to reconfigure the ePLCs on the fly —for example, using different configurations for different sections of a single algorithm —provides valuable flexibility for communications infrastructure applications.

BAZIL is expected in silicon by the first quarter of 2002. Given the diverse algorithms and data rates that increasingly characterize communications applications, heterogeneous architectures like BAZIL will become more mainstream in the near future.

ST's SkyCore Targets Automotive Multimedia
By Jonah Holmes and Jeff Bier, BDTI {7/30/01-03}

At the Embedded Processor Forum in June, STMicroelectronics presented its new SkyCore architecture, a heterogeneous design that combines a 200MHz ST120 DSP and an 80MHz ARM7 general-purpose processor. SkyCore will initially target automotive applications that range from electronic valve control to receiving digital audio broadcasts in a car; according to ST, future derivatives may target portable applications. For some applications, ST will produce SkyCore derivatives with the processor cores running at slower clock speeds. This highly integrated SoC with many specialized I/O interfaces and on-chip peripherals uses the ST120 core for DSP-related tasks while the ARM7 takes care of control functions.

An interesting question about SkyCore is why it uses an ARM7 when the higher-performance ST120 is marketed as having strong general-purpose processing capabilities in addition to its DSP features. ST offered two explanations for this.

First, there is a software consideration. Two different groups outside ST developed the application software, with one working on control tasks and the other handling signal processing. By having each development group use a separate processor, some aspects of the development process may have been simplified by, e.g., reducing unintended interactions between the two pieces of software and isolating hard-real-time DSP tasks from less time-constrained user-interface and supervisory control. Furthermore, using two cores allows ST to run a non-real-time operating system, such as WinCE, for high-level applications while also providing a real-time operating system for DSP tasks. Indeed, given the demanding hard-real-time requirements of DSP applications, software architects often favor this kind of partitioning. However, having two different processors can complicate the hardware and cause difficulties in other aspects of software development.

Another reason ST offered for using the ARM7 is power consumption. According to ST's analysis, overall chip energy efficiency is improved by running control code on the ARM7 and running DSP tasks on the ST120, rather than running both on the DSP. This may be due in part to the fact that the faster memory required by the ST120 is inherently less energy efficient.

Although ST's reasons are plausible, they are not exactly compelling. From the perspective of functionality and performance, the ARM7 doesn't add anything to the capabilities of the ST120. As with TI's OMAP, however, ST may have included the ARM7 in a tacit acknowledgement of the ARM architecture's increasingly prominent role in communications and multimedia applications—a role based in no small part on the mature software development tools, off-the-shelf software components, and other application development infrastructure available for the ARM. While ST has to pay a royalty to use this architecture, the ease with which its customers can use the ARM7 to develop software for SkyCore may very well justify the higher cost.

Microprocessor Forum 2001

Come Celebrate 30 Years of the Microprocessor at Microprocessor Forum 2001
October 15–19, 2001 at the Fairmont in San Jose!

• HEAR first disclosures of more than 20 new microprocessors.
• LEARN about the latest and most advanced architectural concepts.
• NETWORK with the leaders of the microprocessor revolution and see where they are going next.
• ABSORB penetrating insights from award-winning analysts.

• An incredible line-up of new processor introductions
• Look into the future and predictions for microprocessor design for the 21st century
• 3 days of keynotes and sessions
• 2 days of seminars including 2 half-day seminars on Monday October 15th.
• The 14th Annual Microprocessor Report Awards

Is the microprocessor over-the-hill at 30? Where do we go from here?
Find out what happens next at the 14th Annual Microprocessor Forum

Register on line at www.mdronline.com/mpf or call (480)483.4441 (in Scottsdale, AZ)