Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Max Baron, Kevin Krewell, Peter N. Glaskowsky, and Cary Snyder.

In This Issue:

• Editorial: Good Luck Steve Leibson
• Intrinsity’s Dynamic Designs
• Quicker MIPS SoC
• PowerPC 867MHz Fuels New MAC
• MIPS SoCs it to EPF 2001

Of Interest:

• Microprocessor Forum 2001 - News Flash! Conference expanded!
• About Embedded Processor Watch and Microprocessor Watch

Editorial
Good Luck Steve Leibson
By Max Baron {8/27/01-01}

Steve Leibson smiles a lot; it's his way of greeting both good and bad. Those of us who know him can read beyond the smile and see the enjoyment of life, the small pleasures, the stress, and sometimes the pain. When you tickle his funny bone, Steve bursts into laughter with nothing held back, a generous, carefree laugh that puts behind it all worries, a laugh that lets you join in and encourages you to laugh as you used to, many years ago. An avid science fiction fan, Steve has read all the books that deserve reading and beyond. He has watched the movie "Dark Star" and subscribes to Analog and other magazines, which he generously passes on to others. He remembers the plot of every short or long sci fi story and talks eloquently about Schroedinger's cat and parallel worlds and how they might be created or destroyed. The treasured talks extend long into the red sunset, in the darkening quiet office, the temporary refuge from tomorrow's deadlines.

Some of us may remember seeing Steve for the first time, dressed up like one of the Blues Brothers, emceeing MDR's Microprocessor Forum. Dressed in a dark-blue suit and hat and wearing dark glasses, Steve was very different from his predecessors, who imparted to the conference an aura of somber, solemn communication of science and technical achievement. For Steve, MDR's forums are a show to be enjoyed. Steve created rock-and-roll videos dedicated to computing and embedded design and presented them at the MDR forums-songs of praise and encouragement to the modest engineers who shape the world and don't get the recognition they deserve. Steve's show is a brightly colored backdrop for breakthrough technical announcements at the most prestigious computer forums in the world.

Behind the scenes, behind the expensive props is an even more expensive TV-like studio, where a surprisingly large number of people are controlling computers and sound and video and the time-to-finish clock that is displayed for speakers. Steve is there most of the time, half-whispering, coaching speakers, encouraging, making sure that they look their best and that everything happens on time. The speaker is guided up the few steps in the subdued light, the announcer's formal voice performs the introduction, and the speaker is nudged into the intense limelight precisely on time. Steve turns to the next speaker but keeps looking at the time-to-finish clock of the ongoing presentation.

A few months ago, we heard Steve laughing as he watched videos of "battlebots"-battle robots, the remote-controlled engines that fight and destroy each other in specially designed arenas. The arenas can themselves destroy battlebots that carelessly go, or are pushed, into dangerous areas. Steve can watch the videos over and over and enjoy them with a child's pleasure at hearing a story again and again. Looking over his shoulder at the screen, you can't help laughing yourself at the damage these machines can inflict on one another. We weren't surprised that Steve convinced a few battlebot hobbyists to display their engines at the recent Embedded Processor Forum's expo. The battlebots turned out to be a major attraction.

One of our analysts showed me two thick, heavy, expensive steel-cutting saws that he had brought along from a recent trip. "I'm going to use these on a battlebot," he said. I tried not to smile, but my face may have given me away. "I don't have time to actually do it myself," he said, "I may give it to somebody to build it for me." Sure. Yeah. Steve-stuff is getting contagious.

Steve allowed and encouraged us to expand Microprocessor Report's coverage into the embedded processor area in addition to the traditional focus on general-purpose processors for desktop and server applications. Somehow, the shows at the forums, the accent he has put on imagination, his science fiction, and our own coverage of the new embedded systems have all come together at the right time and have propelled the forums and our newsletter into the twenty-first century. For the next Microprocessor Forum, Steve has already created the lyrics for a song about the Itanium. But a lot more work is required to perform and produce it.

Steve joined MDR two years ago, bringing with him his rich and successful background in publishing, 11 years on the editorial staff of EDN, and the sharp understanding of computer systems that he acquired as a design engineer at HP. Steve is a man of impeccable integrity. He is a gentleman of principles, a person you would like to emulate but might find the effort to do so beyond your will power. He is an idealist who has not given up on his principles and inspires the respect of all that know him.

Steve Leibson is our editorial director, MicroDesign Resources' Vice President of Content-"What's VP of Content?" he keeps saying, "I'll say I'm the VP." -but not for much longer. Steve is leaving MDR.

We wish him well.

(Ed.-Steve's last day at MDR was 8/17/01)

Intrinsity’s Dynamic Designs
Fast14 Technology Touted for 2GHz Processors
By Peter N. Glaskowsky {8/13/01-02}

It's axiomatic in the microprocessor business: simple is fast. But simple microprocessors aren't always faster than complex microprocessors. Process technology and design effort can have a greater influence on chip speed than microarchitectural simplicity

What if there were a way to achieve high clock speeds without exotic fabs or vast design teams? What if a small company could create a 2GHz RISC processor using synthesized logic and standard memory cells on a commercial ASIC process?

Intrinsity intends to find out. The company's "Fast14" technology is a family of design techniques driven by a set of automated design tools that allow extremely high-speed logic to be implemented on standard CMOS chips. Intrinsity believes Fast14 logic can achieve roughly triple the speed of conventional static logic, all else being equal.

Intrinsity has built a test chip with a pair of simple 32-bit CPU cores. In a 0.18-micron aluminum-interconnect process, the chip yields speeds above 2.2GHz. Intrinsity, however, is well behind other vendors in coming to market. The company will say only that it is developing processors for embedded applications. If it's as easy to design and build a 2GHz microprocessor using Fast14 as Intrinsity claims, the company should have no lack of customers. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0813/153302.html ).

Quicker MIPS SoC
One-Time-Programmable MIPS Core
By Cary D. Snyder {8/13/01-02}

The number of programmable-logic-based system-on-a-chip (SoC) device families using embedded MIPS processors has been doubled by QuickLogic's joining Altera in offering a MIPS Instruction Set Architecture (ISA) SoC architecture (see MPR 10/16/00-01, "Embedded Processor World War"). In June 2001, QuickLogic announced that its upcoming QuickMIPS architecture is joining its Embedded Standard Product (ESP) family of ASSP/programmable devices. The QuickMIPS architecture features a fully characterized MIPS 4Kc "Jade" processor core with a number of system-support components. The goal for this first chip is for it to be a cost-effective, high-performance programmable SoC.

The concept of a programmable platform FPGA is not unique but is a further sign of a developing trend. The first FPGA vendor to announce hard-processor cores was Altera; Xilinx soon followed. Other announced products from ASI (see MPR 4/30/01-01, "MSA 2500"); Triscend (see MPR 11/16/98-02, "Triscend E5 Reconfigures Microcontrollers," and MPR 9/11/00-03, "Triscend Rolls Out 32-Bit Configurable SoC"); and Actel offer further signs that the developing trend is here to stay. The combination of embedded processors, support functions, and programmable logic creates what MPR calls hybrid programmable SoCs.

QuickLogic offers an approach that differs from that of either Altera or Xilinx. QuickMIPS features a one-time-programmable (OTP) large-gate-count FPGA that has common integrated peripherals embedded as hard IP blocks. These blocks contain the MIPS32 4Kc processor plus peripheral devices like multiple Ethernet MACs, support peripherals (timers, UARTs), memory controllers, and bus interfaces.

The primary advantage of QuickLogic's Eclipse programmable fabric is the higher speeds it offers at a lower cost than standard SRAM-based FPGA technology. The higher speed is due to OTP interconnects or fusible links. The primary disadvantage of QuickLogic's Eclipse programmable fabric is that it is OTP: reprogramming a part is impossible, either in system or by reusing a relatively expensive part. The QuickMIPS devices will use proven Eclipse technology fabricated on a 0.25µm five-layer-metal process that employs QuickLogic's patented ViaLink technology. The balance between the advantages and disadvantages of this architecture makes for an interesting analysis and is the primary focus of this article. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0813/153301.html )

PowerPC 867MHz Fuels New MAC
By Kevin Krewell {8/27/01-02}

Although it keeps inching toward 1GHz, the PowerPC MPC7450 (G4) processor is not there yet. The most recent speed grade of the G4, 867MHz, was launched in the latest Apple G4 Macs at MacWorld on July 18, 2001. The Power Macs are available in three configurations: a dual 800MHz G4, a uniprocessor 867MHz G4, and a 733MHz G4. All three Power Mac G4 models feature 256K of L2 cache per processor, running at full processor speed. In addition, the 867MHz system has 2MB of L3 back-side cache, running at one-quarter the processor speed, and the dual 800MHz Power Mac G4 has one 2MB back-side L3 cache per processor.

The MPC7450 die is fabricated in the HiPerMOS 6 (HiP6) 0.18-micron copper process technology. At 106mm2 with the on-chip 256K L2 cache, the G4 is the same die size as the Pentium III (Coppermine). The 867MHz MPC7450 has a list price of $435 in 1,000-piece quantities. The latest G4 is also available at 800MHz, 733MHz, and 667MHz for $400, $374, and $341, respectively, in 1,000-piece quantities. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0820/153402.html ).

MIPS SoCs it to EPF 2001
MIPS ISA Dominates EPF
By Cary D. Snyder {8/20/01-01}

MIPS Technologies had a great deal of exposure at this year's Embedded Processor Forum (EPF), with six first-time announcements of new cores and MIPS instruction-set-architecture (ISA)-based chips. The June 12 session on high-performance 64-bit system-on-a-chip (SoC) cores started with Morton Zilmer, MIPS Technologies' engineering manager of 5K development, giving the first public presentation on the company's newest MIPS64 5Kf 64-bit core. In its first major announcement in a year and a half (see MPR 10/25/99-05, "MIPS Plays Hardball With Soft Cores"), MIPS announced a new core revision with significant enhancements, which include a floating-point unit (FPU).

The session on 32-bit SoC cores, given the same afternoon, started with Larry Hudepohl, MIPS's director of 32-bit core development, giving the first public presentation of the company's new MIPS32 4KE family, featuring its next-generation 32-bit core family. New features and enhancements include MIPS16e code compression; addition of a coprocessor interface; additional clock-gating options; a write-back cache option; and expanded PC and data trace, with the cache-size range increased to support a 64KB option.

Four MIPS Technologieslicensees made major product announcements at EPF. NEC Electronics, a long-standing proponent and licensee of the MIPS architecture, introduced its VR5500, the newest of NEC's MIPS-based 64-bit processors. PMC-Sierra introduced the RM9000x2, its first multicore processor from the newly formed PMC-Sierra MIPS Processor Division (formerly QED). BRECIS Communications made its first announcement of a multiservice processor chip during the Network Processor Forum, part of EPF. BRECIS presented its newest network processor chip, based on the MIPS32 4Km core. As a startup company, BRECIS focuses on developing a new class of powerful but cost-effective broadband network processors. Alchemy Semiconductor participated in the Information Appliance Processor session. Alchemy, a fabless startup that took a license for the MIPS architecture in 1999, unveiled two new integrated processor chips, the Au1000 and Au1500 SoCs, both targeted at Internet edge devices. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/0820/153401.html ).

Upcoming Events of Interest

Microprocessor Forum 2001 News Flash

Due to the overwhelming number of first time introductions planned at this year conference, we have decided to begin the conference one half day early. The conference will now begin on Monday October 15th at The Fairmont Hotel in San Jose, CA.

Here is what's happening:

• Tuesday's schedule was so jam packed with 1st time introductions that we had to add an extra half day to the conference.
• Conference now set to begin on Monday October 15th at 1:00 pm.
• Register before August 31st for the early bird discount.

This is one event you will not want to miss, so register now while you're thinking about it! Complete program details and fast on-line registration are available now at www.mdronline.com/mpf, or call us toll-free at 800.527.0288 or (480.483.4441(AZ) outside North America).