Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Max Baron, Markus Levy, Chris Van Gaal, Peter N. Glaskowsky Charlie Hauck, Charlie Cheng, and Cary Snyder.

In This Issue:

• SmartMIPS for Smart Cards
• ManArray Devours DSP Code
• MIPS Architecture Enhancements
• What Has Emerged From the Chaos?
• Intel's New Approach to Networking
• VLSI Implementation of a Portable 266MHz 32-Bit RISC Core
• Editorial—Forecasts

SmartMIPS for Smart Cards
The MIPS Technologies Low-Power Challenge
By Cary D. Snyder {10/1/01-02}

There are processor architectures that are known for their low-power attributes, but the MIPS ISA is not one of them. This situation may change if MIPS Technologies can successfully introduce its SmartMIPS architecture; it has been working on creating this architecture with Gemplus SA, the leading smart-card OEM, for more than a year. MIPS Technologies has released its first product and is shipping its MIPS32 4KSc smart-card core, based on its SmartMIPS architecture.

The billion-dollar question remains: Is the smart-card market big enough for processor-core vendors to turn a profit where OEMs must meet a total cost target of $4 per unit? The smart card, by its ubiquity in many countries and growing need in others, is likely to become the most common computing platform worldwide. The role a 32-bit processor plays in this platform is important and cannot be overlooked. Increasing security requirements and the need to run key operating systems indicate there is a healthy market for 32-bit processors. The complete article highlights the technical attributes that make it so.

Magnetic strips, both the key to and weakness of a highly centralized architecture, are also a security issue: plastic cards with these strips have become easy targets for illicit use. Alarming increases of credit card skimming with pocket hand-skimmers in Asia and the western United States are forcing U.S. credit card companies to take rapid action. International travel will also need a way to check a person’s true identity with a secure and fraud-proof system-an electronic passport.

Smarter smart cards that support a variety of secure identity validations and credit- and bankcard transactions represent an attractive solution. The card owner- frequently, the service provider or the user’s own government-must be attracted by being able to offer its customers varying levels of service in a highly secure manner at the lowest overall cost. The smart card is well on its way to becoming the world’s largest single computing platform.

(The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/1008/154101.html)

ManArray Devours DSP Code
BOPS Applies SIMD, VLIW, and Parallel Processing Techniques
By Markus Levy {10/8/01-01}

MDR recently went backstage with BOPS to analyze the company’s ManArray architecture and the capabilities of the company’s newly released Halo compiler. For the practical demonstration of ManArray’s benefits, MDR used the EEMBC benchmarking process, to illustrate the interactions among the architecture, the BOPS development tools, and sample code.

In the tests referenced in this article, MDR examines the BOPS C-optimized and assembly-coded benchmarks. Most interesting is the analysis of the EEMBC Autocorrelation and FFT (Fast-Fourier Transform) benchmarks, because the compiler can achieve maximum optimizations on the former benchmark, whereas hand optimizations are required to maximize performance of the FFT. (The hand-optimized version is 3.4 times faster than the C-optimized version.) The article describes the transformations made on the Autocorrelation and FFT algorithms to achieve peak performance on the BOPS architecture.

The sidebar "Highlights of BDTI’s Analysis of the BOPS ManArray" provides an alternative, and complementary, analysis. In 2000, BDTI evaluated a 2x2 configuration of the BOPS ManArray architecture (in a simulated version of the BOPS Manta chip), using BDTI's DSP algorithm kernel benchmarks optimized in assembly language. Sixteen-bit fixed-point data was used in the benchmark implementations, because this is the data type most likely to be used for classical DSP algorithm kernels on the Manta.

(The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/1008/154101.html).

MIPS Architecture Enhancements
MIPS32 and MIPS64 Pick Up Some Real-Time Features
By Markus Levy {10/22/01-01}

On October 17, 2001, at Microprocessor Forum 2001, Mike Uhler from MIPS Technologies discussed his company’s 2002 plans to evolve the MIPS32 and MIPS64 architecture. There are four focuses of this evolution. The first, and most generally applicable, is inclusion of real-time interrupt and exception-handling mechanisms. Second is expansion of the instruction-set architecture (ISA) to adopt a variety of bit-field manipulation instructions. The third focus is on implementing a more flexible and efficient memory- management system. Finally, the architecture evolution includes a more-flexible coprocessor interface that allows system designers to mix, and not match, processors and coprocessors that have the same or different datapath widths.

(The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/1022/154301.html ).

What Has Emerged From the Chaos?
Update on the State of the Electronics Industry
By Chris Van Gaal {10/22/01-05}

To say that these are uncertain times may be the understatement of this new century. As members of the global high-technology community, we find ourselves in an unprecedented situation, one in which assessing the health and outlook of the world's electronics sectors has become a daunting task at best. The widespread economic weakness that was apparent before the events of September 11, 2001, has been exacerbated, and any resurgence in strength during the near term is questionable.

But despite the chaos of these uncertain times, we are able to arrive at some solid conclusions that will aid in evaluating our prospects for the coming year. All things are comparative as we attempt to arrive at plausible market scenarios for 2002. Bear in mind that even if we experience some return to economic stability during the first half of 2002, we cannot expect any of the semiconductor segments to pick up where they left off in 2000.

(The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/1008/154101.html).

Intel's New Approach to Networking
Follow-on to IXP1200 Features New Cores, New Organization
By Peter N. Glaskowsky {10/22/01-03}

Although details are scarce, Intel’s preview of a next- generation network-processor architecture at the October 18 Network Processing session of Microprocessor Forum 2001 promises to move the company into the sweet spot of the competitive network-equipment market. The new architecture, a highly evolved version of that used in Intel’s IXP1200, provides the basis for a new network- processor chip aimed at 10Gb/s (OC-192) networking equipment.

The new chip will combine Intel’s XScale processor core with multiple microengines for packet processing. The new microengines, though derived from those in the IXP1200, run much faster: 1.4GHz or better in a 0.13-micron process, the highest clock rate of any announced network processor.

Multiprocessor pipelines are not a new idea, even in networking. Cisco’s Toaster 2 uses a pipeline of identical cores, the same approach the new Intel chip takes. Intel, however, believes its new design provides unmatched flexibility for distributing tasks and data among the available microengines. This flexibility could give the new chip an edge over other network processors for 10Gb/s routers, even though some of these competing products may reach the market before Intel’s new chip arrives in 1H02.

From what we learned at the Forum, Intel clearly intends to compete effectively at the high end of the network- processor market. We’ll revisit the company’s products and plans when the new chip is announced.

(The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/1022/154303.html).

VLSI Implementation of a Portable 266MHz 32-Bit RISC Core
By Charlie Hauck and Charlie Cheng, Lexra {10/22/01-04}

While Intel pushes Pentium 4 clock speed past 2GHz, the most pervasive 32-bit RISC cores in system-on-a-chip (SoC) designs are still down in the 200MHz range. For most ASSPs, where the compelling value statement is the system architecture, CPU clock speed has not been a commercial issue. However, two market forces are conspiring to create what may be the most difficult issues facing a fabless semiconductor company using a 32-bit RISC core.

A survey of potential customer need has seen a low level of migration to a 0.15µm process. The speed-demon applications are moving aggressively toward 0.13µm at any cost (and risk), while most other chips are staying behind in the matured 0.18µm process. At the same time, the slowing economy and the DRAM glut mean that 133MHz SDRAM costs literally the same as the 100MHz version. Consequently, a large class of customers has embedded a 32-bit RISC core, is using a 0.18µm process, and requires maximum DRAM bandwidth. These customers now find themselves in a difficult position and require a 266MHz RISC core to maximize system throughput.

This paper describes the way one design team tackled the issues of microarchitecture and VLSI implementation of a 32-bit RISC core that addresses three customer requisites of embedded 32-bit RISC core, 0.18µm process, and maximum DRAM bandwidth. The focus is primarily on clock-speed- related issues; testability, verification, and other issues are touched on only lightly.

(The full version of this article is available online to Microprocessor Report subscribers http://www.mdronline.com/mpr/h/2001/1022/154304.html).

Editorial—Forecasts
By Max Baron {10/29/01}

We keep reading in newspaper business sections, sometimes even on page one, gloom and doom forecasts by presidents and CEOs of semiconductor and OEM companies. We get the same message when we turn to TV for hope. And business and technical analysts reflect the same position. To me, their method of forecasting seems to use the slide-rule approach—not the one used to do math, but the one that slides recovery into the future in increments of years and half- years.

Many experts look upon the recent tragic events as more reasons to push improved-revenue forecasts further into the future. Their pessimistic starting point uses data that shows reduced sales and expectations for corporate and consumer products that are either already out on the shelf or in process of being developed and delivered to market. There seems to be an unstated premise that we should evaluate the future of the electronics business by predicting when "things are going to return to normal" and when life will continue as it did before.

But will life as we used to know it really reboot and return to its previous status? What will the industry do in the meantime? Should the industry, as some pundits suggest, try to survive by holding on to its key employees, spending as little as possible and hibernating until the warm sun of spring comes out?

I don't think so. I think the successful CEOs will look at the short-term scenario and its probable effect on the future. They will respond to the immediate need to help our country a need that may turn into an opportunity to create new business directions or retarget products that, before September 11, 2001, were considered dormant.

A few examples may be in order. Security has become the "product of the hour," creating interest in biometrics, surveillance, smart cards, DNA identifiers, and many other devices that can help decrease potential threats to human life. Previously, security products were aimed at preventing theft of money, goods, and ideas—an important market but, volumewise, unimpressive. Recent events, however, have promoted this type of product to the importance level of health services and beyond. Security products need to run their application programs on desktops and other types of computing systems. Transceivers, digital video, audio, and still-imaging hardware are used in many of these applications. Servers are required to maintain authorization databases and to store accumulated status history.

Recent reductions in travel have reawakened interest in video conferencing and group collaboration over the Internet. Communications hardware and software—distance learning, audio-video streaming, shared whiteboard technologies, and others—that were left dormant for quite a while may now come into their own. The importance of quality-of-service (QoS) and virtual private networks (VPN) will escalate, as QoS and VPN provide quality and confidentiality of communication over the Internet. The distance-collaboration group of products requires desktop computers, servers, whiteboard digitizers, Internet connectivity hardware, video cameras, and real-time streaming services; use of these products will increase the need for more bandwidth in corporate networks.

The scare of dangerous envelopes in the mail will encourage increased use of email and facsimile, enlarging storage requirements at the office and creating penetration of more homes than before. Sales of computing platforms, inexpensive email terminals, printers, fax machines, and Internet connectivity may increase.

The sudden rise of companies in videoconferencing, DNA recognition, and security has occurred because people needed and purchased existing equipment quickly. The need will not soon disappear. New devices with more sophisticated specifications, and others with lower prices, will be welcome, as long as they are delivered in a timely fashion.

We must underscore the important difference between peacetime markets and the type of market we are seeing now. Until a few months ago, product introduction, customer acceptance, and volume sales followed a slow pattern. Many OEM designers budgeted for about 10 to 15 months of development and debug. The follow-on steps of productization, advertising, fabrication, and sales may have brought the total time from design start to solid revenue to about three years.

Recent events have changed the scenario: a sudden market has been created by new circumstances rather than by the introduction of new toys. People have new problems and require immediate solutions; they will respond quickly to their introduction. OEMs must now react in months instead of years. New products must be designed and tested quickly, a requirement that favors use of general-purpose and DSP computing platforms, FPGAs, and appropriate ASSPs. Existing products—such as desktops, servers, and cameras—must be retargeted into quick solutions to new problems. Microprocessors, DSPs, microcontrollers, FPGAs, and other complex semiconductor devices will be needed.

The new business scenario has not replaced the old one but superimposes on it a component the industry can and should act upon. There is a need for quick-turnaround solutions that solve and anticipate problems that may even sacrifice low price for rapid time to market. And instead of complaining, some companies may want to leave the hibernation mode and investigate the current landscape.

Max Baron