Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Max Baron, Kevin Krewell, Markus Levy, and Peter Glaskowsky

In This Issue:

• Editorial – General Purpose Architecture
• ARM Shakes Hands With DSP
• Corrent's Job: Security
• Gigahertz UltraSPARC III SPEC Surprise
• BOPS Announces New Performance Levels
• DCT Marches Into Java Processors
• MPR's Analyst Choice Awards
• Of Special Interest:
  • Embedded Processor Forum 2002
  • Keynotes by Sir Robin Saxby—Executive Chairman, ARM
    and John Bourgoin—Chairman and CEO, MIPS Technologies

Editorial – General Purpose Architecture
By Max Baron {12/31/01-02}

It's no longer possible to assume you can design a processor without having a good idea of the system architecture in which it will be used and the workload it will execute. A large number of designs have become application specific; they can provide higher performance with less of a power requirement than equally priced general-purpose engines.

What happened to general-purpose architecture? Did it become extinct a long time ago with the introduction of floating-point coprocessors? Did it disappear when OS support, such as shadowing registers and register windows, was added? Was it always a myth? Can architectures still be called "general purpose" if they must add MMX, SSE, 3DNow, DSP, Java enhancements, Viterbi instructions, and other extensions?

Recently, I was told about the introduction of a new chip that boasts multiple general-purpose processing cores. As always, I asked the microprocessor vendor what applications the new chip was targeting. The marketing person's answer was not the only one of its kind: "We don't know what software they (our customers) will be running," he said, "but if they use our multiple on-chip processing cores they can get better performance than with only one core."

This general-purpose, application-indifferent approach may have been sufficient several years ago, when it was very hard to design and make processors. Just a few processor architectures were around. The differences between an embedded processor and a desktop processor were price, simplicity of implementation (microarchitecture), and performance. The embedded processor was designed to be inexpensive. Its modest performance was adequate for tasks that were less demanding than those required of the desktop processor.

Today, to survive and prosper, both desktop and embedded processors have to track applications. They are evolving in different ways and following different roadmaps. They employ different architecture and microarchitecture enhancements, conditioned by the technologies they can afford to use.

Desktop microprocessors use state-of-the-art semiconductor technology and design to get the highest possible performance through enhancements to frequency and microarchitecture. Their evolution is driven by the need to present a simple, system-independent programming model to a large base of software applications writers. However, increased frequency doesn't always help, and vendors need to make periodic architectural enhancements as applications become more demanding for improved performance and have the need to process new data types.

Embedded microprocessors, limited as they are by price- acceptable ASIC technology, use both enhancements in architecture and additional processors. What the embedded processor can't obtain through raw frequency and multiple pipe stages, it achieves via special ALU units, additional instructions, accelerators, and hardwired logic. Complex chips that use multiple microprocessor (MPU) and digital- signal processor (DSP) cores and accelerators can deliver performance at lower frequencies and with low power consumption. To top it off, with processing resources in place, designers can increase a chip's chances of success by adding application-specific peripherals. The peripherals count in some chips runs into the tens.

The resulting software development target is complex; programmers must juggle the management and control of multiple on-chip resources. However, the software is created by only a relatively small group of programmers, for whom documentation and support are within the capabilities of an OEM. One look at processors such as Motorola's Dragonball, Intel's IXP1200, and some of TI and ADI's DSP chips proves that processors are designed with specific applications in mind.

Quite a few companies have introduced configurable or extensible instruction-set processors. ARC and Tensilica let designers add special-purpose hardware to speed up processing. Proceler takes a different route: it can call "soft" hardware into existence to accelerate parts of a workload that require high performance. Altera, Xilinx, Triscend, and others provide microprocessor cores and raw hardware that can be programmed at boot time, or, if time permits, at run time. LSI Logic can now combine programmable and fixed cores on one chip. Chicory (now merged with Parthus) has made the argument that an accelerator can do a better job than an instruction- extended processor from the viewpoint of power dissipation. It makes sense that power management may lower the frequency of a central core while accelerator-based activity using less power is taking place.

In the embedded space, with today's demands and available technology, targeted processor architectures, accelerators, and peripherals have become solutions that, given sufficient engineering time and testing, will produce better results than unchanging general-purpose architectures and higher frequencies. Variations, extensions, and special-purpose architectures will continue to be introduced for different reasons: the workload needs high performance; an OEM may have inherited or acquired a binary or source software that needs to be speeded up; or there is a need to efficiently execute an interpreted language, such as Java.

The new embedded chip is very far from being a "don't care" general-purpose processor. Designers should know what applications they are targeting for their chips and what software will be running to execute those applications. And as hardware and software design tools evolve, embedded architectures will more closely reflect the system workload.

Two years ago Keith Diefendorff wrote an editorial entitled "Are There Too Many Processors?" Keith expressed the hope that the laws of natural selection would eventually reduce the number of architectures, and that just a few good ones would survive. I keep thinking of the wonderful world we live in, with its unbelievable number of different living organisms, each configured to fit into its habitat and to succeed there. Why so many processor architectures? I think the answer is "Because there are so many different workloads."

ARM Shakes Hands With DSP
New TI Devices Combine ARM7 and C54x
By Markus Levy {1/7/02-01}

Two new dual-core chips from Texas Instruments come equipped with a 100MHz 'C54x DSP with a 47.5MHz ARM7TDMI, a host of microcontroller-type peripherals, and a 10/100 MAC. The intercore communication mechanism is handled by the ARM port interface and a partially shared memory subsystem. Each core has its own PLL allowing each core to run at different clock speeds. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0107/160101.html ).

Corrent's Job: Security
Today the Server, Tomorrow the World
By Peter N. Glaskowsky {12/31/01-01}

Corrent announced during December that it has begun sampling two new members of its server-oriented Socket Armor processors. The CR7020 is the more sophisticated of the new products, accelerating secure socket layer (SSL), transport-layer security (TLS), and Internet Protocol security (IPsec) functions. The announcement makes Corrent the only vendor shipping chips that can perform these functions at speeds above approximately 1Gb/s.

Corrent also offers the CR7000, essentially a subset of the CR7020 design, that focuses on accelerating the public-key cryptographic functions underlying SSL. These functions are based on modular exponentiation, a complex mathematical function that cannot be implemented efficiently on conventional microprocessors. A good server CPU can perform hundreds of public-key functions per second, but the CR7020 can handle 5,000 per second, a capability of great value to users of high-end Internet e-commerce servers.

The CR7020 is priced at $350, while the CR7000 is $250; both chips enter production in 1Q02. For more information, visit www.corrent.com. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2001/1231/155301.html ).

Gigahertz UltraSPARC III SPEC Surprise
By Kevin Krewell {1/14/02-01}

Sun pulled more than one trick out of its hat with the introduction of the latest speed grade for the UltraSPARC III. For this most recent 1,050MHz version, Sun used the same 0.15-micron, low-k dielectric TI semiconductor process it previously used for the 900MHz US III.

Sun has not put much credence in benchmark results and has not been an exceptional performer on SPEC benchmarks (see MPR 9/4/01-02, "900MHz UltraSPARC III Ready to Ship"). However, the latest US III produced surprising SPEC numbers, with one benchmark in particular showing an amazing increase over previous Sun benchmarks. The base score of 9,389 for the SPECfp2000 program 179.art is roughly four times the score of its closest competitor, the 800MHz Itanium. The combined SPECfp2000 (base) result of 701 virtually ties the 703 score achieved by the 800MHz Itanium, although it still trails the 1,098 score produced by the 1.3GHz Power 4. Although these new US III results are partially the result of the higher frequency and an improved translation look-aside buffer (TLB), in large part the improvements are owing to a new Forte Developer 7 compiler. The new benchmark results now put the 1,050MHz UltraSPARC III in the middle of the high-performance pack instead of at the end of its tail. The US III at 1,050MHz is scheduled to be available for customer shipments in 1Q02. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0114/160201.html

BOPS Announces New Performance Levels
By Markus Levy {1/14/02-03}

On December 21, 2001, BOPS Inc. announced EEMBC benchmark scores that indicated improved capabilities of the company's new breakthrough Halo compiler (www.bops.com). The primary factor in this performance increase is a new global optimization component that BOPS has brought into its tools flow. Specifically, this component is the VLIW Instruction Memory Allocation (VIMA) tool, which performs a call-graph analysis of the entire program and globally allocates slots in the VLIW instruction memories (VIM). In other words, this analysis can identify potential VIM optimizations that require spanning a set of code modules and may not be visible from within a module. Furthermore, the tool lifts "Load VLIW" instruction sequences out of their position in a function and promotes these sequences to the highest safe location in the call graph (as part of the initialization sequence). This action allows the processor to run these instructions only once for each benchmark. (This action works similarly for real applications, such as 802.11A.)

The complexity of a VLIW processor combined with distributed processing elements requires either a highly skilled assembly programmer or an extremely robust compiler. Relying on the latter tool, BOPS continues to pour significant resources into its compiler; the result of this activity is evidenced by its latest release of EEMBC benchmark scores. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0114/160203.html ).

DCT Marches Into Java Processors
Lightfoot and Bigfoot Processors Offer New Twist to Java Execution
By Markus Levy {1/28/02-04}

The year 2002 is the year for embedded Java. It has passed the stage of marketing hype and is settling into a wider variety of embedded applications than ever before. Java will allow the wireless providers and manufacturers to dynamically deliver applications and services. Java also opens the world of smartcards, and major financial institutions (VISA and MasterCard, for example) agree. Like many others, these vendors further demonstrate the need to break away from the desktop environment in a secure and portable way with e-commerce, on-the-fly banking, and remote networking.

DCT Ltd. is one of the newest processor vendors to enter the embedded Java market with a hardware-based solution. To date, DCT is offering two product lines: Lightfoot and Bigfoot. Lightfoot is a home-grown architecture that combines basic RISC features with an innovative approach to Java execution. Bigfoot, on the other hand, is an ARC Cores processor having modifications to turn this configurable RISC processor into an efficient Java engine. The company initially plans to target the hardware security market for the e-commerce space by focusing on security products (e.g., smartcards and smartcard terminals, network security).

With Lightfoot, DCT has devised an architecture that has explicit support for Java. The most distinctive feature of Lightfoot is its instruction format, which provides a soft bytecode layer to give a system a particular application- specific personality. The Lightfoot architecture implements a modified Harvard architecture; however, it has an 8-bit instruction width, a 32-bit-wide internal architecture, and a 32-bit-wide data memory.

Bigfoot is a combination RISC and Java processor built upon the ARC Cores base architecture. DCT has used the extensibility of the ARC architecture to emulate a stack- based machine. DCT was able to bend the ARC processor with relatively simple logic modifications and additions, with hardware support to convert the processor's register bank into a stack. This is a perfect model for ARC Cores, which is designed to have its base instruction-set architecture extended by any customer. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0128/160404.html

MPR's Analyst Choice Awards
By Max Baron {1/22/02-01}

Each year Microprocessor Report analysts review and evaluate more than 100 microprocessors, digital-signal processors, and application-specific digital machines. The most interesting and innovative products make it into our newsletter, some soon after their proud designers have presented them to the world from the stage of MPR's Microprocessor or Embedded Processor Forum. Then, in the first month of each following year, MPR's analysts gather for the exciting and difficult task of selecting the best of the best.

Looking back at 2001, one of the hardest years for the industry, we at MPR are encouraged by the number of innovative designs that have been brought to successful completion; this feeling is further strengthened by the numerous submittals of abstracts for new-product presentations at MPR's upcoming 2002 Embedded Processor Forum.

The analyst team long ago gave up picking one single best processor, because so many are designed for, and excel in, specific applications that range from desktop computers through handsets and MP3 players. This year's MPR awards will recognize the best processor in 9 categories, each category having three or more nominees competing for the top spot.

Microprocessor Report is proud to present the nominees for its annual awards honoring 2001's best processors:

Outstanding Technology in the Field of Digital Processing:

• Intel Hyper-Threading Technology
• Proceler Dynamically VAriable Instruction seT Architecture (DVAITA)
• Sun Microsystems Laboratories Asynchronous Design Technology
• Theseus Logic NULL Convention Logic (NCL)

Best Digital Signal Processors:

• Analog Devices Blackfin 21535
• Analog Devices TigerSHARC TS101S
• LSI LSI402ZX
• Motorola 8102
• Texas Instruments C6414

Best DSP Cores:

• 3DSP UniPHY
• BOPS WirelessRay
• Infineon Carmel 1000
• LSI Logic ZSP400
• Siroyan OneDSP

Best Gaming Chip Set:

• Microsoft Xbox: Intel Pentium III, Nvidia XGU/MCPX
• Nintendo GameCube: IBM Gekko processor, ATI Flipper
• Sony PlayStation 2: Sony Emotion Engine and Graphics Synthesizer
• PC desktop: AMD Athlon XP, VIA Apollo KT266A, Nvidia GeForce3

Best High-Performance Embedded Processor:

• Broadcom BMC1250
• IBM PowerPC 750FX
• Motorola MPC 7455
• NEC VR 5500
• PMC-Sierra RM9000X2

Best High-Performance Processor Soft Cores:

• ARM 1020E Core
• MIPS Technologies MIPS64 20Kc Core
• Tensilica Xtensa Core

Best Network Processor:

• Agere Payload Plus
• AMCC nP7250
• IBM PowerNP NP4GS3
• Motorola C-Port C-5
• Vitesse IQ2000

Best PC Processor:

• AMD Athlon XP
• AMD Duron
• Intel Northwood (Pentium 4)
• Intel Tualatin (Mobile Pentium III-M)

Best Security Processor:

• Broadcom BCM5840
• Corrent CR7020
• Hifn 8154
• Securealink PCC-ISES

Best Server/Workstation Processor:

• AMD Athlon MP
• Compaq Alpha 21264C 1,001MHz
• IBM Power4/Regatta
• Intel Itanium
• Intel Xeon MP

Upcoming Special Event of Interest

Embedded Processor Forum 2002

This year's keynote speakers will be: Sir Robin Saxby—Executive Chairman from ARM and John Bourgoin—Chairman and CEO from MIPS Technologies.

Embedded Processor Forum is the embedded industry's most important week of the year and it's happening April 29 -
May 2nd in San Jose, CA.

Embedded Processor Forum is the professional's conference for embedded computing technology. Focused exclusively on
microprocessors and related hardware technologies that are driving the embedded industry, the forum is the most important place in the industry to present and hear new chip announcements.

Whether you're designing networks, information appliances, or computer games…whether your application requires low
power, high performance, or DSP technology…Embedded Processor Forum gives you the in-depth technical information you need to make a winning embedded decision.

Presented by In-Stat/MicroDesign Resources

Register on line at www.MDRonline.com/epf/register or call 480-483-4441 (in Arizona)