Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Kevin Krewell, Peter Glaskowsky, and Cary Snyder.

In This Issue:

• Editorial – Free Advice for AMD and Intel
• At Least One Chip Niche Is Secure
• Intel Beefs Up Networking Line
• Stretch Goals for Intel Servers
• Spring '02 IDF Focus is Beyond PCs
• IDF 2002 Features XScale I/O Processor
• Upcoming Special Event of Interest at EPF 2002
• Monday's EPF Welcome Party
• Tuesday's EXPO and CTO Roundtable by MIPS Technologies
• Mini-EPW Survey Says?

Editorial
By Kevin Krewell {3/25/02-02}

Free advice is usually worth what you pay for it. It often comes from people without full knowledge of a situation. It is suspect because if it is so important, so astute, why is it free? Well, at times, we all feel compelled to butt in, and I am no exception. It sometimes takes an outsider to look at a situation and make a common-sense suggestion to clarify the issues involved. In the name of journalistic fairness, I have balanced my suggestions by offering advice to both AMD and Intel in the same editorial.

I believe someone has to point out when the emperor has no clothes, and in this case, the missing clothing is customer demand for AMD's SledgeHammer processor. To be blunt, I doubt there is a significant market for AMD's SledgeHammer, and I think AMD is placing engineering resources on the wrong opportunity. Before I explain why I have come to this conclusion, let me say that I consider AMD's Hammer family an excellent engineering solution. I also see AMD's evolutionary 64-bit migration plan for the x86 instruction set as a good conservative strategy. I believe the ClawHammer processor will gain acceptance as a high- performance processor for desktops, notebooks, workstations, and one- and two-processor servers. AMD probably senses that Intel's Xeon processor is vulnerable because its very deep pipeline and small L1 caches are not efficient on server applications. I have a problem, though, with AMD's chances for SledgeHammer in the low-volume, high-margin, high-barriers-to-entry, and ultraconservative server market for four-way and above processor configurations.

AMD's SledgeHammer is designed for multiprocessing systems that use from 4 to 16 processors. With coherent HyperTransport links between processors, AMD can gluelessly connect arrays of SledgeHammer processors, not unlike the capability of Compaq's forthcoming Alpha EV-7 processor. AMD has stated that SledgeHammer will allow it to penetrate the server market by offering a complete solution, from one processor to many, as Intel does. Although that claim is technically correct, what major OEM would actually design and build a server using SledgeHammer? And, perhaps more important, are any AMD customers asking AMD to build SledgeHammer?

A quick review of the top five server OEMs, which (according to Dataquest) have 70% of the server market, does not provide a promising candidate. Compaq has already committed to Itanium, having killed the future Alpha EV-8. Compaq may shortly merge with HP, and HP co-developed the Itanium architecture, making it very unlikely that HP, or a merged HP-Compaq, would choose SledgeHammer. IBM already has the excellent Power4 and has support for Itanium, giving it no incentive to add another 64-bit architecture. Dell has yet to field any non-Intel solution. Sun is committed to the UltraSPARC architecture but will sell Linux boxes using x86 processors. To avoid competing with Sun's own high-end servers, Sun's Linux boxes will likely be limited to one- and two-processor solutions and be very cost sensitive. Those boxes offer a good opportunity for Athlon MP and ClawHammer. SledgeHammer systems larger than dual-processor systems would be too threatening to the UltraSPARC interests at Sun.

This situation leaves AMD with high-end, tier-two server candidates like Cray, Fujitsu-Siemens, SGI, and Unisys. These smaller vendors would have to spend millions on system design and validation for a processor that has no market share. If AMD is counting on Itanium's eventually failing to be competitive, as its critics have maintained, Intel may still have the rumored Plan B for Xeon—Yamhill. Eventually, 64-bit computing will be essentially free, from a silicon standpoint, and Intel will add extended addressing to the x86 architecture.

A much better return on AMD's engineering investment would be provided by focusing on a new mobile-specific processor. When AMD went from zero market share to roughly 40% of U.S. retail notebooks in 2001, it showed it could swiftly grow market share, given a competitive product. Furthermore, AMD might also be able to leverage the expertise in low-power, high-performance processor design from its recent Alchemy acquisition.

Intel's Banias processor will likely change the market for notebook processors in 2003, when clock speed and core voltage control schemes will no longer be sufficient for a mobile processor to be state of the art. Intel is poised to raise the bar with lower-leakage power management, dual VT semiconductor process technology, and specialized chip-set support with integrated wireless LAN capability. We also expect Intel to have microarchitecture-level power management controls.

The notebook market is growing faster than the market for either desktop PCs or servers. Mobile processors may not have the very high prices of server processors, but mobile is a market in which AMD has had a successful track record and could provide a greater number of its customers with a product they want and will actually use.

The Name Game at Intel

In my last editorial, I railed against marchitecture, but for the moment I would like to embrace one of my favorite marketing games: naming processors. I think this is a timely discussion, because Intel is about to make some major changes in its processor lineup, and I think there's still time to help it make the right choice.

In mid-2002, Intel will take the Celeron product from the P6 generation to the P7 generation (which Intel calls the NetBurst architecture, refusing to get into the generation- number game with AMD). The NetBurst version of Celeron is a new-generation product with a new socket, new instructions, different performance characteristics, and several other innovations. When the change from Socket 370 to Socket 478 versions of Celeron occurs, it should not be done without a clear marking that indicates to OEMs, VARs, and consumers that the "new" Celeron is significantly different from the old one. Intel should add a modifier to Celeron brand name to clearly indicate the distinction. The modifier could (and should) be as simple as a "2" (as it is the second microarchitecture generation for Celeron) or a "4" (a reference to the similarity to Pentium 4) postfix. I cannot sufficiently stress how important I think this clarity will be for Intel's customers.

In addition, in 2002, Intel launches its second 64-bit microprocessor—McKinley. If ever a product needed an image booster, it's Itanium. The obvious name change would be Itanium-2 or Itanium II. Some wags have suggested Anadium, derived from the next element in the periodic table after Titanium. (If Itanium is titanium minus the T, then Anadium is vanadium minus the V.) I'll leave it to the highly paid name consultants to decide whether it should have Roman numerals or Arabic and be hyphenated or not—although I'm fond of the retro Roman numeral version (sans hyphen). If AMD or Intel is reluctant to follow this advice, it does come with a full money-back guarantee.

At Least One Chip Niche Is Secure
Security Processors Sure to Sell in 2002
By Peter N. Glaskowsky {2/4/02-01}

Even before the tragic events of September 2001, the market for security processors was growing rapidly. Today, with the U.S. government and private organizations taking a new look at the costs and benefits of heightened security, new applications for security processors are being created almost daily. The most immediate need is to secure networks that now carry data "in the clear." This trend will occur first in corporate wide-area networks (WAN), where the threat is greatest, but LANs will not be far behind.

Security processors will also become a required feature in wireless networks, storage-area networks (SAN), digital- video networks in facilities (such as airports and corporate campuses) having large numbers of security cameras, and cable-modem systems that broadcast customers' Internet traffic throughout their networks.

We at Microprocessor Report have decided to recognize the importance of this trend by instituting an Analysts' Choice Award for security processors. Our nominees this year are Broadcom's BCM5840, Corrent's CR7020, Hifn's 8154, and Securealink's PCC-ISES.

The most valuable security processors are those that are easiest to integrate into networking equipment and that deliver the highest performance. One chip leads the rest, combining gigabit throughput for private-key cryptography and the fastest public-key acceleration available in a multifunction device. We give the Microprocessor Report Analysts' Choice Award for Best Security Processor of 2001 to Corrent's CR7020.

During its lifetime, the CR7020 will face strong competition from Broadcom, Cavium, Hifn, NetOctave (see MPR 11/5/01-05, "NetOctave Secures SANs"), and, possibly, other companies. The winners will be the companies that act quickly to move cost-effective security processing into the widest range of network equipment, from high-cost enterprise routers to high-volume workgroup switches. It is essential that equipment vendors and component suppliers act quickly to communicate the value of secure networks to end users while the public's attention is focused on security issues. If this goal is achieved, security acceleration will soon become a standard feature-not a rare and expensive option. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0204/160501.html ).

Intel Beefs Up Networking Line
New Chips Help IXP Family Reach New Markets
By Peter N. Glaskowsky {3/18/02-01}

The biggest semiconductor company in the network-processing market now has one of the broadest product lines. Three new members of Intel's IXP family of network processors (NPUs) have joined the three existing models of the IXP1200 to cover a wide range of networking devices, from low-cost customer premises equipment (CPE) to high-dollar edge and core routers operating at 10Gb/s or faster.

Announced at the Intel Developer Forum in February, the IXP425, IXP2400, and IXP2800 each targets a specific segment of the networking-equipment market. The IXP425 is a low-cost integrated processor meant for CPE systems with a few 100Mb/s ports. The IXP2400 NPU, with eight microengines running at speeds up to 600MHz, can handle channel aggregation and edge services at 2.4Gb/s. The new top of Intel's line is the 10Gb/s IXP2800, essentially an expanded version of the IXP2400 with twice as many microengines running at a 1.4GHz clock rate.

Although several startups are ahead of Intel in the race to set NPU speed records, only a few companies have any hope of matching Intel's total effort in this space. IBM and Motorola are clearly in the same league, with Agere and AMCC not far behind. Even if smaller vendors can develop individual NPUs having more performance or features than Intel's best chips, they can't expect to provide the complete solutions that Intel and other first-tier NPU makers do.

Intel has little chance of dominating the networking industry as effectively as it has the PC market, but as the company develops a portfolio of complete, effective networking solutions, its success is assured. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0318/161101.html )

Stretch Goals for Intel Servers
New CPUs Aspire to Even Greater Greatness
By Peter N. Glaskowsky {3/25/02-01}

Although Intel's server processors already lead the world in most measurements of performance and price/performance, the company has no intention of allowing the competition to catch up. New CPUs from Intel are designed to extend Intel's advantage over Sun in the enterprise server market, cut off AMD's entry into the low-end server market, and bring Intel within striking distance of IBM's high-end Power series.

Intel is even competing with itself. The Intel/HP design teams creating new Itanium processors are struggling for market share against the Intel teams working on Xeon chips. At the recent Intel Developer Forum (IDF), Intel announced a 2.2GHz Xeon processor that surpasses Itanium's performance on most typical server workloads. Though 32-bit architectures may be passé for large database servers, Xeon has so far rendered Itanium irrelevant in most server applications.

One of the best bits of news from IDF for Intel's server OEMs is that Intel is once again offering a chip set for entry-level servers. The new E7500 is a close relative of the 870 chip set Intel will announce in conjunction with McKinley. OEMs making Pentium 4-based dual-processor servers no longer have to choose between third-party chip sets and Intel's workstation-oriented 860 chip set with its awkward and expensive RDRAM memory requirement.

The new 2.2GHz Xeon processor is the fastest server CPU in the world for its price, just $615 in OEM quantities, but almost all the new chip's performance advantage over the 1.4GHz Pentium III-S can be ascribed to Hyper-Threading alone.

Also at IDF, Intel released a few more details about the 0.13-micron Madison and Deerfield processors that will follow McKinley in 2003. Madison will feature "up to 6M" of on-die L3 cache and remain pin compatible with McKinley, although we expect its front-side bus to run significantly faster.

At its highest company levels, Intel has nothing to worry about. Whether Xeon wins through strength of numbers, or Itanium wins by having a more advanced architecture, Intel wins. Competing server processors have already lost the low end of the market and are losing the midrange. Intel's competitors will hang on to the high-end 64-bit niche for a while longer, but eventually Intel will also take that away from them. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0325/161201.html )

Spring '02 IDF Focus Is Beyond PCs
By Kevin Krewell {3/25/02-03}

The spring Intel Developer Forum (IDF) had the theme of Advancing the Digital Universe. PCs are a big part of Intel's digital universe, but there was less brand new technology demonstrated and the show proved to be more of an update of programs already revealed in previous forums. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0325/161203.html )

IDF 2002 Features XScale I/O Processor
Integrated XScale Processor Targets Mass Market
Cary D. Snyder {4/1/02-02}

Intel quietly announced, without its usual new-processor fanfare, its newest I/O processor, the IOP321, at the March Intel Developer Conference (IDF). The IOP321 I/O Processor is Intel's fifth-generation I/O processor and its first integrated I/O processor using the XScale micro- architecture.

The IOP321 features of the IOP321 a higher level of integration over its two-chip IOP310 predecessor, resulting in significant reductions in system board space use. The name of the game in I/O processors is bandwidth. The new chip also increases system data throughput by using a 200MHz, 64-bit internal bus; an internal 200MHz, 64-bit DDR SDRAM memory controller; and a 133MHz, 64-bit PCI-X interface.

The new IOP321 consumes about 4.0W at 600MHz, an improvement over the IOP310 chip set, which consumed about 7W of power at 733MHz. The new XScale processor core operates at 400MHz or 600MHz, and Intel claims it is code compatible with the IOP310.

In addition to its PCI-X interface, the IOP321 processor features a 32-bit local bus, which is primarily a way to connect to non-PCI peripherals like the processor subsystem's flash memory port and any simple device that can use one of the interface's six chip selects. The 200MHz, 64-bit PC200 DDR memory controller supports up to 1GB of 64-bit or 512MB of 32-bit memory, with or without ECC. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0401/161302.html )

Upcoming Special Event of Interest at EPF 2002

EPF Welcome Party

Sponsored by MIPS Technologies
Monday, April 29 - 5:00-7:30PM
Club Regent, Fairmont Hotel, San Jose

Meet and greet the In-Stat/MDR analysts, industry's movers and shakers while enjoying fabulous food and drink, technical and entertaining interactive demos, and enter to win terrific toys!

CTO Roundtable by MIPS Technologies
Tuesday, April 30 at 7:30PM

After Tuesday's Expo, this year's Premier Industry Sponsor, MIPS Technologies, has gathered a panel of experts that will top off the evening with insightful debate. Hosted by Keith Diefendorff, VP Product Strategy at MIPS Technologies, and Markus Levy, senior analyst at In- Stat/MDR and president of EEMBC, the "CTO Roundtable" will feature senior technical experts from Broadcom, Micron, AMD, Intrinsity, QuickLogic, NEC, PMC-Sierra, and others. The panel is expected to address microprocessor and digital signal processor topics of interest to semiconductor and OEM companies. The panelists will also take questions from the audience.

Embedded Processor Forum is the embedded industry's most important week of the year is April 29 - May 2nd here in San Jose, California.

Embedded Processor Forum is the professional's conference for embedded computing technology. Focused exclusively on microprocessors and related hardware technologies that are driving the embedded industry, the forum is the most important place in the industry to present and hear new chip announcements.

Whether you're designing networks, information appliances, or computer games…whether your application requires low power, high performance, or DSP technology…Embedded Processor Forum gives you the in-depth technical information you need to make a winning embedded decision. Presented by Cahners In-Stat/MicroDesign Resources Register on line at www.MDRonline.com/epf/register or call 480-483-4441 (in Arizona)

Mini-EPW Survey Says?

This is a test to see how many people actually read the 2,900 words above this line.

No, not really. This is a request to participate in a EPW Mini-EPW readership survey. As editor of Embedded Processor Watch I invite readers to send me answers to survey questions like; How can EPW better serve your interests? Or, What topics do you like the best, and the least? Lastly, so it stays a Mini-Survey invitation; How can EPF 2002 best meet your needs as a member of an embedded product design team? Responses can be sent to Cary D. Snyder. cds@mdr.cahners.com. Thanks!