Embedded Processor Watch

Editor: Cary D. Snyder

Contributors to this issue: Peter N. Glaskowsky, Max Baron, Markus Levy and Cary Snyder.

In This Issue:

• EDITORIAL from Editor-in-Chief Peter N. Glaskowsky
• MIPS’ Latest Core Goes Multiprocessor
• NEC Continues Integration Trend
• Ubicom Breaks New NPU Ground
• ARM Family Expands at EPF
• Micron Hitches MIPS and DRAM
• Intrinsity Arrays 2GHz Adaptive Matrix
• EPF Sees More iFlow Info
• Of Interest:
  • Microprocessor Forum 2002: Last Call for Proposals
  • Sample Two Free Microprocessor Report Articles

Editorial
MDR Marches On
By Peter N. Glaskowsky {5/28/02-01}

We've made some significant organizational changes here at MicroDesign Resources. Following our recent Embedded Processor Forum, Max Baron, Microprocessor Report’s editor in chief, requested a return to the position of principal analyst, a title he held at In-Stat before transferring to MDR. I was selected to replace Max as MPR editor in chief, and I will also act as a principal analyst here. All of us at MDR would like to offer Max our heartfelt thanks for all his efforts as editor in chief of MPR, and I'm sure you'll be seeing even more of his writing now that he can focus full-time on technology and market analysis.

Kevin Krewell was also promoted as part of the reorganization. Kevin is now MDR’s general manager and will handle administrative functions in addition to continuing his roles as senior analyst and senior editor of MPR.

I believe these changes will strengthen our organization and enhance our ability to deliver the deep, insightful analysis our customers expect from us. We’ll make no major immediate changes to Microprocessor Report, but I do plan to tighten our focus on microprocessor technology over time. I’m considering a variety of specific changes to implement this plan, and I welcome any feedback you’d like to provide. If you haven’t yet done so, please take the time to fill out our subscriber survey, which is still available at www.MPRonline.com.

I believe Microprocessor Report’s primary role in the industry is to explain advances in microprocessor architecture, as expressed in commercial semiconductor products. Accordingly, we will report on every significant development in this area, whether it is related to PC processors, embedded CPUs, or even microcontrollers. In the early 1990s, for example, architectural progress was concentrated within the workstation space. The techniques developed for RISC microprocessors were later adapted to PC and server processors and were augmented by even more-sophisticated architectural features. Today, embedded processors—especially those aimed at networking equipment—seem to be benefiting most from architectural innovation.

Regardless of where these advances are made, Microprocessor Report will cover them. Within the constraints of analyst time and expertise, the scope of our coverage will include related technologies that influence, or are influenced by, microprocessor architecture. Trends in process technology, system-on-a-chip integration, operating systems and application software-and even chip packaging-can influence CPU evolution. Such developments will receive our attention in proportion to their significance.

Even when it comes to microprocessor introductions-a topic clearly essential to Microprocessor Report—we must prioritize our coverage. High-end server and workstation processors tend to have more-advanced technology, but low-end embedded CPUs sell better, and there are more of them. Which end of the market should receive more of our attention?

To me, there’s no question: Performance is a far better figure of merit for architectural progress than manufacturing cost or sales volume. Improvements to design tools and manufacturing technology ensure that every new feature, no matter its original cost in design time or gate count, eventually becomes affordable, even in the least expensive processors. Sometimes, crucial improvements appear at the low end first and migrate upward; we’ll cover those, too. Do you agree? Let me know.

We are likely to have openings in our editorial board, and I hope to establish relationships with others outside our organization who can contribute articles from time to time. If you're qualified and interested in working with us, please write to me.

Many talented and passionate editors in chief have managed Microprocessor Report over the years, and I am honored to join their ranks. All of us here are committed to making this newsletter the best publication in the microprocessor industry-the first place you turn for the news and insight you need to do your job. With your help, we will.

MIPS’ Latest Core Goes Multiprocessor
MIPS32 Architectural Enhancements Are Part of New M4K Core
By Cary D. Snyder {5/20/02-01}

The latest news from MIPS Technologies highlights an emerging trend: adaptations for chip multiprocessing (CMP) in synthesizable cores. The Embedded Processor Forum 2002 presentation by David Courtright, MIPS Technologies’ director of product strategy, announced the company’s newest and most innovative core to date, the MIPS32 M4K. The significant microarchitecture changes to M4K include removal of all cache control logic to create a cacheless memory interface, improved debug support, improved interprocessor communications, and more configuration options.

Two new M4K design-time configuration options include ability to support user-defined instruction-set (UDI) extensions and selection of from one to four general-purpose register (GPR) sets for fast context switching. Using standard multi-CPU cores with fixed caches for channel or parallel processing tasks can be expensive in terms of both silicon and code size. By adding the cacheless MIPS32 M4K core to its other core families, MIPS is offering its customers more options for using industry-standard processor cores with existing third-party tool support in multi-CPU configurations or for applications requiring a small core. MIPS Technologies’ introduction of the M4K core family proves it is possible to enhance MIPS architecture by employing user-defined instruction-set extensions. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0520/162001.html ).

NEC Continues Integration Trend
MIPS64-based VR7700 Family Introduced at EPF 2002
By Cary D. Snyder {5/28/02-02}

NEC Corporation announced the first member of its newest integrated VR7700 family at Embedded Processor Forum 2002. Starting with the processor core used in its VR5500, NEC has added an integrated level-2 cache, memory controller, PCI-X interface, and other peripherals to create the VR7701.

With the introduction of the VR7700 family, NEC maintains its focus on delivering solid performance for embedded systems at an affordable price. NEC’s roadmap calls for higher-frequency pin-compatible processors in the VR7700 family, which will help it maintain its price/performance leadership in the high-performance embedded-processor market. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0528/162102.html ).

Ubicom Breaks New NPU Ground
IP2022 Expands Network-Processor Market-at the Low End
By Peter N. Glaskowsky {5/28/02-03}

As chip prices come down, sales volumes go up-so dictates the law of supply and demand. It follows that an inexpensive network processor has the potential to outsell all the NPUs aimed at high-end applications. This is Ubicom’s strategy in a nutshell. At Embedded Processor Forum 2002, Ubicom’s David Fotland detailed the company’s IP2022 Internet Edge Processor, a highly optimized NPU for embedded systems. The chip sells for just $13, requires no support chips, and outperforms competing solutions that cost twice as much and use far more board space.

The IP2022 makes some sacrifices to achieve this price/performance edge but is still capable of adding substantial networking capabilities to consumer and office devices. The simple nature of the IP2022 belies its capabilities. Even with both Ethernet interfaces running at 9Mb/s, more than 50% of the core clock cycles are available to customer code. This remaining CPU horsepower is roughly comparable to the full resources of a 50MHz 32-bit RISC processor running typical networking code. Because the IP2022 is scarcely more expensive than two ordinary Ethernet controllers, it’s like getting a 50MHz processor free. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0528/162103.html ).

ARM Family Expands at EPF
ARM11 Microarchitecture Stretches Pipe to Boost Frequency
By Cary D. Snyder {6/3/02-01}

ARM has been under continuous pressure to improve the performance of its licensable core products. The company hopes the ARM11 microarchitecture, introduced at Embedded Processor Forum 2002, will allow its customers to deliver higher-performance ASIC designs using ARM-based cores. ARM’s newest microarchitecture implements the ARMv6 architecture specification. The first soft-macro ARM11-based core should be available by the end of the year. ARM expects these implementations to achieve frequencies up to 420MHz.

ARM is also under increased pressure from its customers for a hard-macro-derived implementation that can reach 1GHz frequencies and beyond. ARM has demonstrated evolutionary enhancements to its ARM-based architecture; nevertheless, its ARM10-based implementation of its V5TE architecture was slow to catch on. Future ARM11-based products should be capable of delivering higher performance than any other ARM architecture. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0603/162201.html ).

Micron Hitches MIPS and DRAM
New Embedded DRAM Architecture Presented at Embedded Processor Forum
By Markus Levy {6/3/02-02}

Micron is setting out to join the business of selling microprocessors combined with some of its DRAM. Micron announced its first product, the SOC-G0, on April 29, 2002, at the Embedded Processor Forum. The embedded DRAM devices contain a MIPS32 4Kc core and a variety of peripherals, including four USB ports, dual ATA ports, and an AC-97 codec interface. The question is this: Has Micron figured out the recipe to make this more than a niche product?

E-DRAM first became available about 10 years ago. Obviously, there are substantial benefits that have kept this technology moving forward, albeit slowly. Those benefits include reduced latency, dramatically increased bandwidth to main memory, reduced power and energy consumption, reduced space, and, sometimes, multiple independent address/data streams. The first product from Micron, based on 8MB of e-DRAM, consists of eight separate 1MB cores, each of which has a 128-bit I/O interface. The small size of the e-DRAM core allows Micron to shave off one clock in precharge and one clock in CAS access. Theoretically, each e-DRAM core can deliver up to 3.2GB/sec bandwidth. Although the maximum bandwidth is limited by the SOC-G0’s crossbar switch (which can handle up to 6GB/sec), the peripherals in this core do not come close to overtaxing the switch. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0603/162202.html ).

Intrinsity Arrays 2GHz Adaptive Matrix
EPF 2002 Presentation Introduces FastMath
By Max Baron {5/13/02-01}

First presented at EPF 2002, Intrinsity’s FastMath, a new real-time adaptive signal-processing applications processor, implemented in 0.13-micron technology, is expected to run at 2GHz. FastMath performs adaptive signal processing via software control and is different from adaptive computing machines that reconfigure hardware to obtain workload-optimized performance. FastMath’s architecture provides, on a single chip, a high-performance digital-signal-processing matrix connected to an L1 I&D-cached MIPS32-compliant core as a tightly coupled coprocessor. The coprocessor is implemented by 16 computing elements, arranged in a 4x4 matrix and capable of broadcasting values to all the elements in its row and column. Each element can use operands from its own register set or from a recent broadcast.

Claimed to deliver up to six times the performance of today’s fastest DSP in executing math-intensive operations, Intrinsity’s chip will target sockets in wireless infrastructure and high-performance image processing for medical, radar, and high-end printer-copier systems.

A Taiwan foundry, unnamed at the time of this writing but leaving just two choices-United Microelectronics Corporation or Taiwan Semiconductor Manufacturing Corporation-will fabricate the processor. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0513/161901.html ).

EPF Sees More iFlow Info
Silicon Access Networks Details iPP Packet Processor
By Peter N. Glaskowsky {5/13/02-02}

Attendees at the recent Embedded Processor Forum 2002 received the most detailed look to date at Silicon Access Networks’ forthcoming iPP packet processor, part of the company’s iFlow network-processing family. The iPP, first announced last fall, has been taped out and is due to begin sampling in June. Silicon Access calls the iPP a "true 20Gb/s network processor," but we view it as a full-duplex 10Gb/s product. With about 50Gb/s of aggregate network I/O, the iPP is comparable to products offered by EZchip and Internet Machines, but it is potentially capable of twice the throughput of 10Gb/s NPUs from AMCC and Terago.

As one of several NPU startups developing 10Gb/s solutions without prior experience at the 2.4Gb/s level, Silicon Access lacks the momentum of companies such as AMCC, Intel, and Motorola, which are much larger and already well established in the market. Silicon Access will have to deliver a complete solution all at once and prove itself to potential customers faced with many alternatives.

Silicon Access will offer the iPP in speed grades of 266, 300, and 333MHz. The chip will be priced below $1,000 in 1,000-unit volumes. (The full version of this article is available online to Microprocessor Report subscribers at http://www.mdronline.com/mpr/h/2002/0513/161902.html ).

Upcoming Events of Interest:

Microprocessor Forum 2002: Last Call for Proposals

MicroDesign Resources is accepting presentation proposals for the fifteenth annual Microprocessor Forum, October 14-17, 2002, Fairmont Hotel, San Jose, California.

We will consider proposals from companies making announcements of new high-performance microprocessor technology. Presentations must include significant technical detail and include new information not previously disclosed. Microprocessors disclosed in detail for the first time will be given preference. Areas of interest include processors for PCs, processors for workstations and servers, embedded processors, network processors, DSPs, and programmable multimedia processors. Contact: trumpf@mdr.cahners.com

There are other opportunities for companies to participate, including exhibits and sponsorships. For information, contact the Microprocessor Processor Forum event manager at dmendelson@mdr.cahners.com (707.933.8854).

See our web site for more details: http://www.mdronline.com/mpf/

Sample Two Free Microprocessor Report Articles

Download TWO FREE Microprocessor Report Articles from the leading publication in microprocessor technology. Enjoy two complimentary articles from the award winning Microprocessor Report by analysts Max Baron and Kevin Krewell. See what you are missing!

Access the free full stories here: http://www.mdronline.com/downloads/mpr_articles.htm