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Issue #151 -- 06/24/2002
Editor: Kevin Krewell, kkrewell@reedbusiness.com
In this issue:
Peter Glaskowsky - Editor-in-Chief {06/24/2002}
We at Microprocessor Report have been conducting
a reader survey online, in person, and by telephone since earlier
this year, and we want all of you to know we value your comments
and suggestions. Please keep this input coming, even after we stop
asking for it. This feedback is providing one basis for changes
we hope will improve the quality and relevance of our newsletter
and the associated Microprocessor Forum and Embedded Processor Forum
conferences. Many of you are both our clients and the suppliers
of our most valuable raw material - information - so I'll also explain
how you can make the most of both aspects of our relationship.
We've changed some of our coverage areas, in part because of the
departure of In-Stat/MDR analyst Cary Snyder. Markus Levy has assumed
the role of primary analyst for high-performance embedded processors.
Markus's new assignment aligns well with the other half of his professional
life, the presidency of the nonprofit Embedded Microprocessor Benchmarking
Consortium (EEMBC). Markus works with the leading embedded-processor
vendors in both capacities, and we believe this relationship benefits
both organizations.
In-Stat/MDR principal analyst Max Baron will now focus on low-power
embedded processors, including those aimed at demanding consumer-electronics
applications such as PDAs and cell phones. Low-power processors
tend to have smaller transistor counts than do their high-performance
cousins, but they require the same leading-edge circuit design and
manufacturing technology. System designers give these processors
typical power budgets of less than a quarter of a watt but insist
on PC-desktop levels of interactivity and signal-processing performance.
Our colleague Kevin Krewell has more on his plate than the rest
of us. Kevin is MDR's primary analyst for PC, server, and workstation
processors and is the author of the reports published by In-Stat/MDR's
Intel Microprocessors Service. As I reported last month, Kevin is
also MDR's general manager - a full-time job in itself.
In addition to my responsibilities as editor in chief of Microprocessor
Report, I'll be helping Kevin by covering the architecture of high-end
microprocessors, with occasional articles about PC-platform technology,
my original coverage area at MDR six years ago. I will continue
to cover other topics as well, including networking, graphics, and
media processing. As with all our coverage, I'll be most interested
in products illustrating microprocessor - technology critical trends
that extend beyond individual chips.
If you're with a company that makes microprocessors - or any product
or technology that works with, depends on, or enables microprocessors
- we want to hear from you. We can't cover everything that happens
in the microprocessor industry, but we will often report on topics
outside our primary coverage areas. The evolution of process and
packaging technology, operating systems and application programs,
peripheral devices, and usage trends substantially affects the way
microprocessors are designed and used.
The email addresses of all our analysts can be found on the Microprocessor
Report masthead and at www.MDRonline. com. These addresses should
be used for direct communication with the individual analyst - to
set up briefings, for example. All distribution lists for press
releases and other material, even if they fall into a specific coverage
area, should now be addressed to mdr-pr@reedbusiness.com. We'll
sort this material at our end and make sure the appropriate analysts
see it.
If you have comments about MDR content, including Microprocessor
Report articles, the Intel Microprocessors Service, and Forum presentations,
please write to mdr-comments@reedbusiness.com. All our analysts
will read these comments, and we will provide a personal response
when needed.
If you'd like to suggest topics for coverage in Microprocessor Report
- or possibly write something for the newsletter yourself - please
write to mdr-mpr@reedbusiness.com. We can't accept articles written
by vendors about their own products, but if you have an independent
viewpoint on a topic of importance in the microprocessor industry,
please send us a brief description of what you'd like to say. We
request that you contact us before submitting complete manuscripts
or confidential information, however.
When we write an article for Microprocessor Report, we generally
need a week for the initial research and a week to write the first
draft, which is distributed to the analysts and Microprocessor Report's
editorial review board on a Friday. Most articles are also offered
for technical review to the vendors of the products discussed in
the piece. This vendor-review process is central to Microprocessor
Report's goal of providing accurate and complete information. Of
course, our analysts draw their own conclusions from the facts supplied
to them. Analysts provide the final draft of each story to our production
staff ten days after the review draft, and, after final review and
proofreading, stories go online on Monday, one week later.
This whole process takes about four weeks from start to finish.
With sufficient advance notice, we can publish articles about your
company's announcements on the Monday morning after your press release
comes out - and on the same day for Monday announcements. As we
have always done, we honor all embargo dates and nondisclosure agreements.
We've received many excellent proposals for presentations at Microprocessor
Forum 2002, to be held October 14-17 in San Jose. If we accept your
proposal, we're likely to write about your chip or technology in
Microprocessor Report. To ensure prompt coverage of your company's
announcement, please schedule advance briefings with the appropriate
analyst about six weeks before the conference. Newsletter articles
on Forum announcements can be published on the same day the presentation
is given.
MDR analysts are available for consulting work and on-site seminars.
Please contact the individual analyst or Kevin Krewell for more
information.
Last, but equally important: members of the print and broadcast
media are welcome to contact us for comments and insight on industry
news. "Press quotes" are a valuable marketing tool for us, and we
like to think they improve the quality of press coverage, too.
I hope you don't mind my hijacking our normal editorial slot for
this one-time-only administrative note. I welcome your comments
and questions at png@reedbusiness.com.
Editorials are available online at:
http://www.mdronline.com/mpr_public/index.html
Markus Levy - Senior Editor {06/24/2002}
Digital video and imaging are among the
fastest-growing areas in the electronics industry. Applications
include cellular phones and PDAs, digital cameras (still and motion),
portable streaming-video appliances, set-top boxes, and security
cameras. For optimal performance, these applications all rely on
a processor's ability to take advantage of data-level parallelism.
At the Embedded Processor Forum 2002, a new fabless semiconductor
company, ChipWrights, described its scalable architecture designed
to tackle the specific demands of video and imaging. The architecture,
named CWvx, is actually the combination of two processors - a proprietary
RISC processor and an application-specific DSP - organized to function
as a SIMD/vector machine.
Microprocessor Report readers can access the full story here: http://www.mdronline.com/mpr/h/2002/0624/162502.html.
Peter Glaskowsky - Editor-in-Chief {06/17/2002}
IBM's new PowerPC 440GX is the latest in
a series of embedded processors produced through the company's Blue
Logic ASIC program. The 440GX is based on IBM's superscalar PowerPC
440 core, the 128-bit CoreConnect bus architecture, and several
other licensable intellectual property (IP) cores. All the expertise,
design tools, and process technology used to create the 440GX are
available to any customer.
As a standard product, the 440GX will build on the success of the
440GP in networked office equipment and similar applications. The
new chip's higher performance and new features will open new markets
for IBM, and the added TCP/IP acceleration will let the 440GX compete
against otherwise similar products that have higher CPU clock rates.
The company has a long way to go if it hopes to match the breadth
of Motorola's embedded offerings, but the 440GX clearly shows that
IBM has the flexibility to expand its reach.
Microprocessor Report readers can access the full story here: http://www.mdronline.com/mpr/h/2002/0617/162401.html.
Max Baron - Principal Analyst {06/17/2002}
Lenslet, an Israeli startup, unveiled details
of its first DSP product, the EnLight256, at Embedded Processor
Forum 2002. Lenslet claims its new DSP will be able to deliver up
to 8 tera (T = 8 x 1012) MAC operations per second by integrating
an optical digital signal processor with a vector processor unit
(VPU) and a DSP core. The company is developing products it hopes
will find sockets in wireless and cellular base stations and in
applications such as smart antennas for wide-band CDMA (WBCDMA)
transceivers, machine vision, video compression/decompression, and
voice recognition. Lenslet states it can deliver software tools
and reusable code to increase the efficiency of writing code for
the engine. The tools provide hardware abstraction of native instructions
and are aware of the timing relationships that must exist between
the EnLight256's internal cores.
Microprocessor Report readers can access the full story here: http://www.mdronline.com/mpr/h/2002/0617/162402.html.
Max Baron - Principal Analyst {06/10/2002}
At the recent Embedded Processor Forum (EPF
2002), Intrinsity, a fabless company founded in 1997 and headquartered
in Austin, Texas, unveiled FastMIPS, a chip based on a MIPS32-compliant
core that is claimed to run at 2GHz and is expected to be available
in sampling quantities before the end of 2002.
Expected by MPR to be manufactured by Taiwan Semiconductor Manufacturing
Corporation (TSMC), the new chip, in addition to targeting wireless
infrastructure, will compete for market share in routers, switches,
network security, and other applications.
The new engine will take advantage of the company's Fast14 technology
to attain the 2GHz frequency and will be connected to a 1GHz, 1MB
instruction and data L2 cache. The L2 cache will be served by an
SDRAM controller that can connect it to an external DDR-400 SDRAM
and by a 4GB/s interconnect fed by two 1GB/s full-duplex RapidIO
ports.
Microprocessor Report readers can access the full story here: http://www.mdronline.com/mpr/h/2002/0610/162301.html.
Peter Glaskowsky - Editor-in-Chief {06/10/2002}
At the recent Embedded Processor Forum,
NEC and Toshiba announced all-new internally developed media processors
they hope will find broad applications in digital multimedia and
communications.
NEC's uPD77050, aimed at cell-phone handsets and other low-power
applications, is officially labeled a DSP but features a classic
media-processor architecture: a four-way 16-bit VLIW core feeding
40-bit general-purpose registers. The 0.13-micron chip runs at 250MHz
with a 1.5V core supply or at 180MHz with a 0.9V supply. NEC estimates
the 77050 will consume about 0.225mW/mips on the 1.5V supply and
just 0.081mW/mips when running on 0.9V. These figures are based
on a nominal 4-mips/MHz rating. NEC plans to sell the chip for under
$30 in quantity; sampling begins 3Q02.
The Media Embedded Processor (MeP) from Toshiba achieves similar
results from a somewhat more flexible and synthesizable design.
Toshiba starts with a fairly conventional 32-bit RISC core having
a five-stage pipeline supporting 16- and 32-bit instructions and
adds a VLIW coprocessor to perform multimedia processing. The VLIW
coprocessor can be configured at design time to execute two or three
instructions in parallel through a 32- or 64-bit instruction SIMD
datapath. The datapath can process 8- or 16-bit values in parallel
for each operation. Clock rates as high as 300MHz are expected from
a 0.13-micron process. Toshiba has not announced pricing or availability
for the MeP.
Microprocessor Report readers can access the full story here: http://www.mdronline.com/mpr/h/2002/0610/162302.html.
Markus Levy - Senior Editor {06/10/2002}
The use of packet-switched telephone networks
avoids wasted bandwidth and has resulted in a breadth of semiconductor
products, specifically DSPs, that handle voice over packet (VoP)
algorithms. One of the many vendors producing VoP cores is Netergy
Microelectronics, a subsidiary of 8x8, Inc. At the Embedded Processor
Forum 2002, Netergy announced its seventh-generation DSP engine,
the Audacity-VP7. The Audacity-VP7 combines a RISC engine with a
single-instruction multiple-data (SIMD) DSP coprocessor. The RISC
engine functions as the main controller, supplying flow control
and address generation for the DSP section. The DSP section, typical
of any DSP, has an ALU and a MAC, each of which can simultaneously
perform four operations per cycle on four contiguous 16-bit values
in memory, packed into 64-bit fields. Netergy's strategy, which
is similar to that of most VoP vendors, is to provide both the hardware
and software components to support the VoP application. But Netergy
has some stiff competition. What gives them the edge?
Microprocessor Report readers can access the full story here: http://www.mdronline.com/mpr/h/2002/0610/162303.html.
Cary D. Snyder {06/03/2002}
ARM has been under continuous pressure to
improve the performance of its licensable core products. The company
hopes the ARM11 microarchitecture, introduced at Embedded Processor
Forum 2002, will allow its customers to deliver higher-performance
ASIC designs using ARM-based cores. ARM's newest microarchitecture
implements the ARMv6 architecture specification. The first soft-macro
ARM11-based core should be available by the end of the year. ARM
expects these implementations to achieve frequencies up to 420MHz.
ARM is also under increased pressure from its customers for a hard-macro-derived
implementation that can reach 1GHz frequencies and beyond. ARM has
demonstrated evolutionary enhancements to its ARM-based architecture;
nevertheless, its ARM10-based implementation of its V5TE architecture
was slow to catch on. Future ARM11-based products should be capable
of delivering higher performance than any other ARM architecture.
Microprocessor Report readers can access the full story here: http://www.mdronline.com/mpr/h/2002/0603/162201.html.
Markus Levy - Senior Editor {06/03/2002}
Micron is setting out to join the business
of selling microprocessors combined with some of its DRAM. Micron
announced its first product, the SOC-G0, on April 29, 2002, at the
Embedded Processor Forum. The embedded DRAM devices contain a MIPS32
4Kc core and a variety of peripherals, including four USB ports,
dual ATA ports, and an AC-97 codec interface. The question is this:
Has Micron figured out the recipe to make this more than a niche
product?
E-DRAM first became available about 10 years ago. Obviously, there
are substantial benefits that have kept this technology moving forward,
albeit slowly. Those benefits include reduced latency, dramatically
increased bandwidth to main memory, reduced power and energy consumption,
reduced space, and, sometimes, multiple independent address/data
streams. The first product from Micron, based on 8MB of e-DRAM,
consists of eight separate 1MB cores, each of which has a 128-bit
I/O interface. The small size of the e-DRAM core allows Micron to
shave off one clock in precharge and one clock in CAS access. Theoretically,
each e-DRAM core can deliver up to 3.2GB/sec bandwidth. Although
the maximum bandwidth is limited by the SOC-G0's crossbar switch
(which can handle up to 6GB/sec), the peripherals in this core do
not come close to overtaxing the switch.
Microprocessor Report readers can access the full story here: http://www.mdronline.com/mpr/h/2002/0603/162202.html.
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