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Issue #152 -- 07/29/2002
Editor: Kevin Krewell, kkrewell@reedbusiness.com
In this issue:
Peter Glaskowsky - Editor-in-Chief {07/29/2002}
It's been a terrible year for the semiconductor
industry, at least on the sales side. Almost every chip maker has
reported reduced sales volumes, revenues, and (especially) profits.
We've all heard executives say they know this situation is just
temporary, the industry will bounce back, and their companies are
continuing to invest in developing the processes and products we'll
need when the market recovers. These are the right things to say,
but what have these executives been doing?
It looks as if they've been doing what they say they've been doing.
When we requested proposals for presentations at Microprocessor
Forum 2002, we were unsure what we'd get. If the industry had been
scaling back its research and development spending, we might be
offered a lot of rehashed reviews of old chips - or, at best, some
minor updates to existing designs.
Instead, we received more than 70 proposals, and the vast majority
involved substantially new and innovative chips. We were offered
more first-time announcements than I can recall for any recent Forum.
We decided early this year not to attempt a repeat of the marathon
three-and-a-half-day conference of MPF2001. If we had, however,
we still could have filled the program with interesting presentations.
Instead, MPF2002 will have the best two-day program in years. We'll
see introductions of new desktop, mobile, and server processors;
a slew of new 10Gb/s network processors; and embedded processors
covering a wide range of market, performance, and price targets.
Many of the chips we couldn't fit into the program will be covered
here in Microprocessor Report, time and space permitting.
This year marks our fifteenth Microprocessor Forum, and we're pleased
to announce that MDR founder Michael Slater will return to give
a talk about the Forum's history. Microprocessor Report editorial-board
member Nick Tredennick will make his fifteenth annual Microprocessor
Report Awards presentation, continuing his streak as the only person
to present at every MPF, and, of course, we'll have four excellent
seminars split across the days before and after the conference.
I can't say much about the proposals we've accepted; you'll have
to come to the Forum for the full details. I can say we're now seeing
more cross-fertilization in the industry than ever before. Fewer
and fewer microprocessors are pure implementations of a single concept.
PC processors are borrowing features from server chips; embedded
processors are being extended into media processors; and network
processors are adding a little bit of everything.
With 70+ proposals competing for about 20 slots, we were forced
to turn down many worthwhile presentations. We regret this, but
we know the Forum represents a significant investment of time and
money by our presenters, attendees, and sponsors. We want to make
sure this Forum, like every Forum, provides everyone with the best
possible value.
Which leads me to a related topic. With microprocessor developers
investing in new products to lead them out of the doldrums, now
may be the right time for us to expand our conference business.
We believe that by next year, our industry will be restored to its
former state of health and robust growth. Should we add more tracks
to our existing conferences? Should we add a third conference to
the schedule? We could even do an overseas event, reaching microprocessor
designers and their customers in Europe or Asia.
Your comments and suggestions on this matter would be most welcome;
just drop me a note: png@reedbusiness.com. Time is of the essence;
if we're to set up a new event in 2003, we must move quickly. Should
we decide to add a new conference, expect to hear about it in October
at MPF2002.
Editorials are available online at:
http://www.mdronline.com/mpr_public/index.html
Peter Glaskowsky - Editor-in-Chief {07/22/2002}
Improv Systems has released a second-generation
customizable VLIW media-processor core, building on the company's
earlier Jazz architecture. The new Crescendo core is offered in
the form of a "solution kit" that provides all the tools necessary
for customers to adapt the core to their particular requirements.
The kit includes application software, system-on-chip integration
tools, and bus models for ARM and MIPS processor interfaces, plus
the AMBA on-chip interconnect, a verification environment, and a
reference platform.
Improv's goal in creating these solution kits is to provide complete
solutions - and that's what Improv will need to do to succeed in
this business. Improv (www.improvsys.com) is up against other media-processor
companies, such as Equator; media-processor efforts at major semiconductor
companies, such as NEC and Toshiba; and competing configurable-processor
vendors, such as ARC, MIPS, and Tensilica.
Some customers, seeking ease of implementation over efficiency and
scalability, will stick with simple RISC cores. Improv's offerings
must be as easy to understand, implement, and support as any of
these are, and they must match or beat the overall solution cost.
Crescendo shows that Improv understands what it has to do; it's
now up to the market to judge the results.
Microprocessor Report readers can access the full story here: http://www.mdronline.com/mpr/h/2002/0722/162901.html.
Peter Glaskowsky - Editor-in-Chief {07/15/2002}
Rambus has revealed the third major element
of its Yellowstone signaling technology, which will be used in next-generation
specialty memory devices for graphics cards, consumer electronics,
and networking applications. The company's new FlexPhase circuit
technology, which was demonstrated at the Rambus Developer Forum
in Japan in early July, uses per-pin delay generators to compensate
for skew.
FlexPhase is initially targeted to memory subsystems that approximate
point-to-point configurations - just one or two memory devices attached
to each data line. The Yellowstone databus works with a command/address
bus that does not use FlexPhase.
Although Rambus is devoting its initial Yellowstone marketing efforts
to applications in memory systems, we believe the technology is
appropriate for other chip-to-chip signaling uses. The new technology
will be of great interest to makers of game consoles and networking
equipment, where the demand for performance is almost insatiable.
We doubt Rambus can push Yellowstone into main-memory applications
without a powerful patron - and Intel is unlikely to provide such
patronage, as it did with RDRAM - but Yellowstone should succeed
in many other markets on its own merits.
Microprocessor Report readers can access the full story here: http://www.mdronline.com/mpr/h/2002/0715/162801.html.
Markus Levy - Senior Editor {07/15/2002}
Riding on the coattails of StarCore's recent
announcement that it will become an independent supplier of DSP
cores (see MPR 7/1/02-02, "StarCore LLC"), the DSP Group has announced
a significant expansion of its product offerings. Although most
of the world does not know it, in 2001 the DSP Group was number
one for licensed DSP cores with its Oak, Palm, Teak, and TeakLite
products. The expansion, similar to that announced by ARM on June
19, 2002, with its PrimeXsys platform, is the DSP Group's inclusion
of a general-purpose subsystem with its processor cores.
The DSP Group's subsystem, called XpertTeak, is a fully synthesizable
and process-independent megablock containing the dual-MAC Teak DSP
Core, on-chip data and program memories, a DMA controller, a buffered
time-division-multiplexing (TDM) port, a host-port interface, a
serial I/O interface, a general-purpose I/O interface, timers, an
interrupt controller, and support for runtime debugging. The gate
count for the megablock is 310K, excluding memory.
At the beginning of this article, we mentioned StarCore to point
out that, as a competing DSP intellectual property (IP) vendor,
the DSP Group is several steps ahead of StarCore, which has not
yet made any peripherals or megablocks available. Although this
situation should not be considered a discredit to StarCore, as it
is a new company, the lack of a supporting subsystem will delay
the architecture's acceptance. On the other hand, the strength of
the StarCore infrastructure with Agere, Infineon, and Motorola has
the potential of quickly leapfrogging the DSP Group's XpertTeak,
at least in the general-purpose DSP business.
The DSP Group is light-years ahead of StarCore, however, in terms
of application-specific SoCs and software support. The company's
portfolio includes voice-over-packet and imaging software and hardware.
The DSP Group is also one of the companies that developed the G.723.1
speech technology that is now licensable through the International
Telecommunications Union (ITU). In addition to this portfolio, the
DSP Group's licensing business has been spun off as a wholly independent
subsidiary and has acquired Parthus LLC. Coupled with the Parthus
merger, the new megacore announcement will help make the DSP Group's
IP economy resistant.
To help its customers accelerate software development, the DSP Group
offers the XpertTeak IP in silicon format. Implemented using the
0.18-micron TSMC technology, the chip runs at up to 200MHz, consumes
11.8mW, and is already available to licensees of the XpertTeak IP.
We believe this chip offers limited benefit to customers, because
the customer must still develop a custom ASIC to implement any proprietary,
value-added intellectual property. In other words, if the XpertTeak
is in fact a "ready-made" megablock and the customer were building
an SoC, the extra effort of integrating the DSP portion would be
incremental. Furthermore, as a general-purpose DSP chip, the XpertTeak
directly competes against devices from Analog Devices and Texas
Instruments.
For more information on DSPs, go to www.MPRonline.com.
Peter Glaskowsky - Editor-in-Chief {07/08/2002}
Silverback Systems has announced a new family
of programmable network processors optimized for storage networks
rather than for Internet-style data-communications networks. The
iSNAP line of Internet Protocol storage-network-access processors
begins with the iSNAP2100, which is designed to connect a pair of
Gigabit Ethernet networks to high-speed disk and tape systems. The
same chip can also be used to connect file servers to storage networks.
The 2100 includes two Gigabit Ethernet interfaces that can also
be used to connect to other high-speed serial interfaces; one bidirectional
SPI-3 interface that provides a link to an optional 2.4Gb/s switch
fabric; and a 64-bit, 133MHz PCI-X port with a sustained throughput
that exceeds 800MB/s. The chip accelerates TCP/IP and iSCSI processing
using five MIPS 4KE processor cores that are assisted by several
specialized function units.
The iSNAP2100 probably won't enable new classes of products, but
it should greatly improve the performance of existing products.
If Silverback can demonstrate such an advantage to potential customers,
it should have no trouble selling its chips.
Microprocessor Report readers can access the full story here: http://www.mdronline.com/mpr/h/2002/0708/162701.html.
Peter Glaskowsky - Editor-in-Chief {07/08/2002}
The latest vendor to join the 10Gb/s packet-processing
market is Sandburst, a startup first funded in October 2000. Sandburst's
HiBeam switching architecture will be implemented initially in a
four-device chip set. Three chips - the SE-1600 switching engine,
the BME-1600 bandwidth-management engine, and the QE-1000 queuing
engine - comprise the HiBeam packet fabric.
The fourth chip, the FE-1000 forwarding engine, acts as a configurable
- that is, not fully programmable - network processor. The chip
executes proprietary microcode developed by Sandburst to process
up to 25 million packets per second. The advantage of Sandburst's
configurable solution is that customers need not write custom software
for the HiBeam platform. The disadvantage is that Sandburst's customers
cannot write custom software for the HiBeam platform.
Sandburst expects to sample the complete chip set in 3Q02. General
availability is scheduled for 4Q02. Pricing was not announced. For
more information, visit www.sandburst.com.
For the latest news on microprocessor technology, go to www.MPRonline.com.
Rich Belgard {07/01/2002}
In a May 28, 2002, ruling, expected by patent
lawyers for some time, the Supreme Court handed down its decision
on one of the most important patent cases in recent years, the case
of Festo v. Shoketsu Kinzoku Kogyo Kabushiki Co. (aka SMC). The
Festo case has to do with a common-sense principle in patent law
called 3prosecution history estoppel.2 This rule means that if a
patentee, in an effort to get her/his claims allowed, tells the
patent examiner the claims are in some way limited in scope, the
patentee cannot later take a contrary position in trying to prove
infringement.
A lower-court ruling in late 2000 previously held that if a patentee
modified elements of the claims for patentability reasons during
prosecution of a patent, then those elements must be literally present
when trying to prove infringement.
The Supreme Court essentially reverted to the law as it was before
Festo and ruled that prosecution history estoppel may apply to any
claim amendment, but it does not prevent the use of the equivalents
in an infringement lawsuit. The result is that technology patents
can again be applied more broadly, using 3equivalent2 elements.
Many of the patents we have, or are likely to see, have regained
a degree of power they temporarily lost in the initial Festo decisions.
Microprocessor Report readers can access the full story here: http://www.mdronline.com/mpr/h/2002/0701/162601.html.
Markus Levy - Senior Editor {07/01/2002}
One is a lonely number. Two is a couple.
Three is a crowd - or is it? For the past several years, Infineon
has single-handedly tried to use its Carmel DSP to compete in the
market for DSP intellectual property cores. Likewise, Agere Systems
and Motorola, as a team, have attempted to expand the StarCore architecture
and use it in chips the two companies developed independently.
On June 18, 2002, the three companies announced they have jointly
formed a limited liability company named StarCore. The new company,
to begin operations during September 2002, will be based in Austin,
Texas, but the design and development offices will be in Tel Aviv.
We don't want to cast doubt on the success of the new StarCore LLC,
but it should be noted that the company has quite a bit of work
in store. For starters, the existing cores will have to be made
user friendly, to make them easy for external customers to integrate
into their SoCs. The core product family will also have to be expanded.
Specifically, a dual-MAC core should be developed, as this seems
to be the sweet spot for current-generation DSPs. Furthermore, let's
not forget development tools. To be successful on the open market,
the StarCore architecture must obtain a variety of development tools,
either proprietary or through third parties. Robust, production
grade, highly-optimizing DSP C compilers with world-class integrated
development environments has become an important consideration for
customers looking to spend long nights developing important products.
Microprocessor Report readers can access the full story here: http://www.mdronline.com/mpr/h/2002/0701/162602.html.
Markus Levy - Senior Editor {07/01/2002}
Java processors continue to proliferate
(despite the few that will soon be extinct). Most recently, Vulcan
Machines, neighbor to ARM Ltd. in Cambridge, England, announced
its second-generation Java processor, the Moon 2. Last we heard
from Vulcan Machines was at Microprocessor Forum 2000, when the
company presented some details of its Moon 1.
Moon 2 executes Java bytecodes in hardware as its native instruction
set; hence, there is no translation before execution of the code.
The processor can be attached to a host core as a coprocessor, providing
a hardware replacement for a software Java Virtual Machine (JVM).
In this respect, it is similar to DCT's Lightfoot, Nazomi's JA108,
and Zucotto Wireless's Xpresso 100, meaning it incorporates such
features as a standard bus interface and support for interprocessor
communication. However, Moon 2 can also function as a standalone
Java processor.
Moon 2 is packed into about 27K logic gates and must be supplemented
with a minimum of 3KB of ROM plus 1KB of SRAM. The Moon 2 core,
with caches and on-chip memory, typically consumes 0.25mW/MHz when
implemented in a low-power 0.18-micron process. In a standard 0.18-micron
process, power consumption doubles. Without accounting for any layout
optimizations, this 0.18-micron process yields a core that can operate
up to 100MHz. Although Vulcan claims its processor consumes one
bytecode per clock, the true system-level performance is an unknown.
The company is actively involved with EEMBC in helping to define
the first set of embedded-Java benchmarks.
Moon 2 is available now for licensing in VHDL for integration into
an SoC and netlist for FPGA instantiation. A Verilog version is
on Vulcan's roadmap.
For the latest news on microprocessor technology, go to www.MPRonline.com.
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