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Issue #154 -- 09/30/2002
In this issue:
Peter Glaskowsky - Editor-in-Chief {09/30/2002}
October will see the fifteenth annual Microprocessor
Forum, something of a milestone for us at Microprocessor Report.
None of us now at MDR attended the first Forum, but many members
of our editorial board were there. Board member Nick Tredennick
has presented at every Forum, and he'll be there again this year.
Nick graciously lent us his collection of Microprocessor Forum proceedings--oddly,
we didn't have a full set here in the office--and it makes interesting
reading.
While preparing for this special anniversary, I learned that the
first MDR conference--held in November 1988--was Microprocessors
'89, a naming strategy that the following year gave way to the now-familiar
Microprocessor Forum scheme. Most presenters at that first
conference returned for later events. Over the years, Forum has
achieved a high degree of continuity in its speakers. We are pleased
that so many speakers and panelists at MPF2002 have participated
in previous Forums. Such experience helps us develop and present
long-term perspectives on industry trends.
One such trend is the victory of RISC principles over the CISC implementations
that dominated the industry until the 1990s. The RISC proponents
who spoke at Forums over the years were absolutely correct: RISC
is the best foundation for combining a fast, efficient CPU with
advanced compiler technology. The RISC philosophy has achieved tremendous
success, although it hasn't exactly been the irresistible force
its advocates hoped it would be.
Because of its success in the PC processor market, Intel in particular
was able to spend billions to adapt RISC technology to its CISC
architecture. Year by year, Microprocessor Forum documented this
process. The Forum made it much easier for attendees to understand
the way the processor market developed in the 1990s.
As important as the RISC vs. CISC battle was, the overall growth
of the market led to an even more important development. Market
segments that were once too small to support their own processor
architectures--such as data communications, multimedia, and laptop
computers--may now choose from several optimized alternatives. I
attended my first Microprocessor Forum in 1995. That was the first
Forum to devote so much time to application-specific processing.
MPF95 had presentations from several vendors of media- and communications-oriented
processors, including John Moussouris of MicroUnity, which trademarked
the term MediaProcessor for its CPU.
Since then, instruction-set complexity has become almost irrelevant.
Not only are the fastest clock rates on the market achieved by x86
chips, but some of the most interesting CPUs in the world have instruction
sets of unbounded complexity: almost any logic function a customer
can specify can be built into an ARC or Tensilica core and given
its own opcode.
Microprocessors have evolved to take advantage of the parallelism
inherent in almost any algorithm, whether that parallelism exists
in data, instructions, threads, or processes. Because some algorithms
possess some types of parallelism but not others, we'll probably
never see a CPU that outperforms every other processor on all applications.
Future Microprocessor Forums will document this evolution. Dozens
of processor architectures were on the market in 1988, and hundreds
are available today. I'm convinced that thousands of distinct designs
will exist fifteen years from now, most of them proprietary implementations
created for specific products. The details of so many designs will
be outside the scope of Forum, but their common foundations--the
science and engineering that makes them possible--will remain Microprocessor
Forum's central focus.
To find out more about Microprocessor Report and Microprocessor
Forum, please visit: www.mdronline.com.
Peter Glaskowsky - Editor-in-Chief {09/30/2002}
In-Stat/MDR is pleased to announce that
Dr. Donald Alpert, architect of Intel's Pentium processor, has been
named to the newly created position of MDR Fellow. Dr. Alpert will
write articles for the Microprocessor Report newsletter and participate
in In-Stat/MDR's annual Microprocessor Forum and Embedded Processor
Forum conferences. As an MDR Fellow, Dr. Alpert will also become
part of Microprocessor Report's editorial board, joining other industry
luminaries who contribute their experience and insight to every
issue of the newsletter.
Dr. Alpert will work with Microprocessor Report's editor in chief
Peter N.Glaskowsky and the rest of the MDR analyst staff to prepare
in-depth technical analysis articles for the newsletter. These articles
are expected to focus on emerging new high-performance microprocessor
architectures in all segments of the market--from PC and server
processors to embedded systems.
In addition to his role as architecture manager on the Pentium project,
Dr. Alpert has more than 20 years experience as a microprocessor
architect for Zilog, National Semiconductor, and Intel. Dr. Alpert
earned his Ph.D. in electrical engineering from Stanford University
and has been extensively published in industry journals. He holds
27 patents related to processor design.
To find out more about Microprocessor Report, please visit: www.mdronline.com.
Tom R. Halfhill - Senior Editor {09/23/2002}
Once available to only a few favored customers,
Texas Instruments' dual-processor OMAP family is now represented
by a standard product. (These days, TI rarely spells out OMAP, which
stands for Open Multimedia Applications Platform.) The new OMAP5910
chip unites a slightly modified ARM9TDMI microprocessor core with
a TMS320C55x DSP core plus a generous amount of on-chip memory and
a host of useful peripherals.
TI is offering the OMAP5910 for embedded applications that need
real-time control processing and data-intensive signal processing.
Examples might include vertical-market PDAs, biometrics, telematics,
car audio systems, and medical equipment. TI has privately supplied
previous OMAP incarnations--the OMAP310, OMAP710, and OMAP1510--to
Hewlett-Packard, NEC, Nokia, and Palm for 2.5G/3G wireless phones
and wireless-communicator PDAs.
Microprocessor Report readers can access the full story here:
www.mdronline.com/mpr/h/2002/0923/163801.html.html. To find
out more about Microprocessor Report, please visit:
www.mdronline.com.
Tom R. Halfhill - Senior Editor {09/16/2002}
Tensilica is shipping the fifth version
of its configurable soft microprocessor core since 1999, adding
new features and enhancing some existing ones. According to Tensilica's
simulations, the new Xtensa V core should run at 350MHz (worst-case)
when fabricated in a 0.13-micron CMOS process. Tensilica says some
Xtensa V configurations will run even faster and that improvements
to the company's proprietary hardware-design language and C/C++
compiler can boost actual software performance by 50% over the Xtensa
IV.
The Xtensa V revisions are not a major overhaul, but they do affect
the architecture at every level. There are new features in the processor
core; new functions in the Tensilica Instruction Extensions (TIE)
language; and new optimizations in the Xtensa C/C++ compiler (XCC).
When considered as a whole, Xtensa V introduces some worthwhile
features and improvements.
Certified EEMBC results confirm that Xtensa V has posted the highest-ever
score in the consumer benchmark suite and excellent scores in the
networking and telecommunication suites. However, one drawback of
Tensilica's EEMBC benchmarks is that they are based on simulations,
not actual silicon. Spinning a custom chip for the sole purpose
of running EEMBC benchmarks is too costly for processor-IP vendors.
It's possible for the simulations to stray from reality, as we discovered
when comparing Tensilica's scores to the certified EEMBC scores
reported by ARC International, a rival configurable-processor vendor.
Microprocessor Report readers can access the full story here:
www.mdronline.com/mpr/h/2002/0916/163701.html. To find out more
about Microprocessor Report, please visit:
www.mdronline.com.
Peter Glaskowsky - Editor-in-Chief {09/16/2002}
LSI Logic recently announced RapidChip,
a new way to make system-on-chip (SoC) devices that combines design
techniques from FPGAs, ASICs, and application-specific standard
products (ASSPs). It may be easiest to think of these new products
as "semi-standard" chips, built on a standard foundation using standard
methods, but finished to meet customer needs.
Three platform families are initially available for communications,
storage, and consumer products. These platforms are offered in LSI
Logic's 0.18- and 0.11-micron processes. The company says designs
are underway in both processes, and will start to be manufactured
early next year. By the end of 2003, customers can start developing
90nm RapidChip products. More information is available at rapidchip.lsilogic.com.
To find out more about Microprocessor Report, please visit:
www.mdronline.com.
Max Baron - Principal Analyst {09/03/2002}
MIPS Technologies has introduced a family
of new system controllers for system-on-chip (SoC) designs that
should help entrepreneurs create new products more quickly than
ever, using the MIPS 4K, 5K, synthesizable cores and the 20K core.
The new SOC-it controllers offer flexible on-chip interfaces to
intellectual property, connectivity to Advanced Microcontroller
Bus Architecture (AMBA) peripherals, optimal core-memory interfaces,
and PCI compatibility.
The architecture of SOC-it resembles an ARM Multi-Layer AMBA
high-speed bus (AHB) interconnect that has been implemented for
two layers. Additional layers could improve SOC-it, but many designers
using it will find that two layers deliver sufficient performance
improvement for their systems. MIPS claims that an FPGA-based simulation
of a chip using SOC-it demonstrates a 20% performance improvement
over one that has a less-efficient interface to memory.
Microprocessor Report readers can access the full story here:
www.mdronline.com/mpr/h/2002/0903/163502.html. To find out more
about Microprocessor Report, please visit:
www.mdronline.com.
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