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Issue #155
-- 10/28/2002
Editor: Tom R. Halfhill
In this issue:
Don Alpert
{10/28/2002}
The latest ColdFire core implements two execution pipelines for full superscalar organization along with improved hardware branch prediction. Motorola also enhanced the instruction set with extensions for signal processing and interrupt handling. These collective improvements should enable the ColdFire architecture to continue its success in diverse, high-end embedded applications.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1028/164301.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Peter Glaskowsky - Editor-in-Chief
{10/28/2002}
Without quite announcing specific products, Keith Morris of Applied Micro Circuits Corp. (AMCC) gave Microprocessor Forum 2002 a big hint of what the company has planned for its next-generation network processors (NPU). AMCC’s fifth-generation nP5 NPU technology will add full-duplex communications plus on-chip search and traffic-management units to the basic design of its current products.
The nP5 family will include 5Gb/s and 10Gb/s chips built in 0.13-micron processes and running at higher clock speeds than previous AMCC NPUs, to provide more processing for each packet. AMCC plans to debut the nP5 family in a 5Gb/s device with integrated media access control (MAC) units, much like the company’s current nP3400 chips. This device is code-named nP3XXX. AMCC’s current nP7510, a half-duplex 10Gb/s packet processor that relies on external coprocessors, will also be updated with the new nP5 technology. The resulting product is code-named nP7XXX.
AMCC has a large family of established products to support it while it waits through the current lull in demand. Delaying its next product generation gives the company a chance to create a better product. AMCC did not reveal when it plans to announce or ship nP5 products, but we expect the market to be ready for these new chips by 2H03.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1028/164303.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Peter Glaskowsky - Editor-in-Chief
{10/28/2002}
The following is an adaptation of remarks delivered as my introduction to Microprocessor Forum 2002.
Welcome to Microprocessor Forum 2002, our fifteenth annual fall event. Those of you who attended our first conference in 1988 may recall that it was a RISC-centric affair. There were no x86 processors in the program that year. In 1989, we had our first x86 presentation, and x86 has been a major part of the Forum ever since.
But not this year. For the first time in fourteen years, no x86 processor will be announced here. We have come full circle; the market has moved on.
X86 might still be a major part of our program if not for Intel’s 1994 decision to purchase Digital Semiconductor and adopt the Alpha processor as Intel’s workstation and server processor of choice. Though the purchase may have been forced on Intel by Digital’s threat of litigation, Intel got a great deal. Along with Alpha, Intel acquired the StrongARM processor, a substantial portfolio of communications products, and Digital’s unmatched circuit-design talent. We can see today that Intel’s decision to support Alpha was a turning point in our industry. With Intel’s considerable resources behind it, RISC-based Windows NT took off immediately.
By 1999, RISC-based Windows NT systems had moved out of server rooms to take over the corporate desktop. The transition to NT in home systems has taken longer than expected, but Microsoft’s decision to release only the 64-bit RISC version of Windows XP means the eventual end of x86 PCs. Intel and AMD will sell over 30 million x86 processors into low-end home computers this year—almost 20% of the total PC market—but few Tier One OEMs are likely to introduce new x86 PCs in 2003.
The OEM and end-user preference for Windows XP is behind Intel’s decision, announced early this year, to stop further development of Pentium processors for PCs. Though the 1GHz Pentium 4 is an impressive accomplishment, no amount of tweaking will let an x86 core compete against the 8GHz RISC designs we’ll see today. Intel continues to offer low-end x86 chips for low-margin applications such as information appliances, but we wouldn’t be surprised to see Intel sell off the last of its x86 business within the next year or two.
We have a remarkable variety of presentations for you today, but I’d like to highlight just three. I’m sure you’re all eagerly waiting to hear about Intel’s Alpha EV11, the world’s first massively multithreaded processor architecture. This new design, which will be made in variants supporting from 8 to 32 threads and up to 24 execution units, depending on the target market segment, could very well account for over half of all Intel-based PCs and servers sold in 2004.
As a Mac user, I’m also looking forward to AMD’s disclosure of the PowerPC 680. AMD’s 1995 decision to license the PowerPC architecture certainly paid off. Though most of AMD’s production goes into Windows XP systems, the company competes strongly with both Motorola and IBM for sales into the low-volume but high-prestige Apple Macintosh market.
We’re also happy to have HP-Sun here to present its next-generation EPIC III processor, the latest VLIW implementation of the SPARC instruction-set architecture. As you know, 2002 will see the final shipments of HP-Sun’s PA-RISC and SPARC systems. This commitment to EPIC was a major component of the merger of the two companies in 2001. The new EPIC III processor being announced here today will provide an excellent platform for both technical computing in the HP division and business systems under the Sun brand.
You may remember the rumors from 1994 that Intel was negotiating with HP to co-design EPIC as an x86-compatible VLIW machine. How different the world would be today if that deal hadn’t fallen through…
Okay. Back to reality.
Obviously, that’s not how the world turned out. Aside from the details of corporate alliances, the most striking difference between my little fantasy and the real world today is the strength of x86. Not only is Pentium 4 the fastest and most successful PC processor in the world, but AMD’s plan to extend the x86 architecture for 64-bit computing means we could be looking at another 20 years of x86 PCs and servers. So, for the foreseeable future, x86 will continue to play a major role at Microprocessor Forum. In fact, we had several important x86 presentations at the Forum this year.
All of the RISC architectures that vied for Windows NT system sales in the mid-1990s are still around, but not in PCs. Some still contend for shares of the server business, but only IBM’s Power and Sun’s SPARC seem to have long-term prospects there. The Intel/HP Itanium project has cut the legs out from under Alpha, MIPS, and PA-RISC.
Itanium got off to a shaky start, but it’s standing on its own two legs today and is likely to cover considerable ground over the next several years. Intel has hinted at some remarkable Itanium designs in the works, and we heard more hints in Forum presentations from Intel’s John Crawford and Robert Yung.
In the embedded world, RISC has nothing to fear from x86. Both approaches have natural applications in embedded systems, as we heard on the second day of MPF 2002, but RISC owns most of the overall embedded market. Network processors, media processors, and the best low-power and high-performance embedded processors are all RISC designs.
Microprocessor Forum 2002 was a great success, and we hope to see you all at the next Embedded Processor Forum in June and at MPF 2003 next October.
To find out more about Microprocessor Report, please visit: www.mdronline.com.
Markus Levy - Senior Editor
{10/21/2002}
At Microprocessor Forum 2002, ARM introduced the first two members of its ARM11 family. The new ARM1136J-S and ARM1136JF-S represent the zenith of generations of ARM cores, and, in addition to having backward compatibility, they include new features, such as an integrated direct memory access (DMA) that is tightly coupled to the tightly-coupled memories (TCMs). The ARM1136 cores also support the new SIMD instructions ARM announced in 2001. A new and enhanced MMU has support for application-space identifiers to help avoid flushing the translation lookaside buffers.
The more obvious features of the new products are signaled by their names, with “J” indicating that both products support ARM’s Java accelerator. The “F” betokens the presence of an integrated floating-point unit. The “S” evidences that both new cores are synthesizable, giving customers more flexibility for configuration options.
The decision to produce synthesizable cores also influenced the architecture of the ARM11 pipeline, which was specifically designed to handle compiled RAMs and deliver high-frequency operation by minimizing some of the critical paths. The “E” is no longer part of the product name, but it is implied that all new products include the ARM DSP extensions. (The same is true for the Thumb [“T”] extensions.)
As with previous generations of ARM processors, inclusion of a vector-floating-point (VFP) coprocessor is optional with the ARM1136. However, because of the ARM1136’s higher clock speed, ARM no longer offers the VFP as a separate piece the customer can “glue together”; it is integrated with the core to avoid a potential impact on clock speed. Furthermore, the generic coprocessor interface of the ARM1136 is inherently different from that on previous ARM cores.
The longer pipeline will give the ARM1136 a clock boost over the ARM1026EJ-S; this article contains the various performance and power specifications. The ARM1136 will gain some of the performance through enhanced branch-prediction mechanisms that combine static and dynamic branch prediction.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1021/164202.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Markus Levy - Senior Editor
{10/16/2002}
At Microprocessor Forum 2002, Broadcom announced its BCM1400 quad-core multiprocessor, focusing on the chip’s high-speed buses and I/O subsystem, specifically the on-chip switch, memory bridge, packet DMA, multiprotocol ports with integrated packet managers, and cache-coherent nonuniform memory accesses. The BCM1400 doubles the theoretical processing capacity of Broadcom’s previously announced dual-core BCM1250 containing four MIPS64-based SB-1 cores. The on-chip bandwidth of the BCM1400 is handled by Broadcom’s proprietary 16GB/s internal ZBbus that also maintains coherency among ZBbus agents (i.e., processors, memory, and DMAs). For off-chip communications, as well as for supported coherency for interchip multiprocessing, the BCM1400 also added three 19Gb/s SPI-4/HyperTransport ports.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1016/164101.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Peter Glaskowsky - Editor-in-Chief
{10/16/2002}
At Microprocessor Forum 2002, Cisco rewrote the history of the network processor with the first public disclosure of its Toaster3 (T3) network processor. Brought to life in Cisco’s labs in June 2001, Toaster3 became the first NPU capable of processing a 10Gb/s datastream—some seven months before Terago claimed that title with its ProNP 5010 in January 2002. Although other vendors have since released 10Gb/s devices, Toaster3 is an important milestone in the progress of the network-processor market.
Cisco was in no rush to announce Toaster3. Toaster2 saw its first public disclosure in Microprocessor Report about eight months after the first Toaster2-based systems started shipping. Toaster3, the latest implementation of Cisco’s parallel express forwarding (PXF) architecture, is shipping in Cisco networking equipment today, although the company’s MPF2002 presentation did not disclose which systems contain the new chip.
Toaster3 will not directly affect the merchant market for network processors—except to preclude other NPU vendors from selling into some of the most popular networking systems in the world. By developing its own NPU, Cisco has made the job of independent NPU suppliers much more difficult. These other companies should be thankful for one small favor, at least: Cisco won’t be selling Toaster3 against their products.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1016/164102.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Markus Levy - Senior Editor
{10/16/2002}
Samsung appears to have successfully leveraged experience gained from its famous and deceased Alpha processor. Its newest processor, available in IP core format, is a 1.2GHz ARM1020E core Samsung calls Halla. At Microprocessor Forum 2002, Samsung presented the circuit design techniques it used to triple the clock frequency above the typical operating frequency obtained by the out-of-the-box ARM1020E. This new core will also temporarily steal the ARM performance lead from Intel. Furthermore, except for the anticipated 2GHz MIPS32-based processor from Intrinsity, Samsung’s core will rank at the top of the performance charts for scalar embedded processors.
Samsung has been an ARM licensee for eight years, including some unmodified ARM7 and ARM9 cores directly within custom ASICs and ASSPs. In designing its new ARM1020E processor core, Samsung applied some interesting circuit-design techniques while maintaining cycle-accurate compliance with the original ARM1020E.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1016/164103.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Peter Glaskowsky - Editor-in-Chief
{10/07/2002}
The structure of future PCs and servers became clearer at September's Intel Developer Forum (IDF). A mix of standards—some originating with Intel, some from other industry groups—has emerged as the consensus choice of chip, board, and system makers.
We expect that by 2004, the PC platform will rely almost entirely on serial links for communication between major peripheral subsystems. Future PCs will be easier to configure and maintain by virtue of these new standards, and new PC form factors are sure to emerge as industrial designers come to appreciate the flexibility that longer, thinner interconnects permit.
Wireless links between devices—such as BlueTooth, 802.11, and ultrawideband (UWB)—will also play a role in future systems. Intel described its efforts in these areas, and unveiled plans to increase its support for wireless communications. So-called Wireless MMX extensions will be added to Intel's XScale processors, and Intel will add silicon-germanium (SiGe) transistors and other radio-frequency (RF) circuitry to its 90nm process.
Clearly, Intel is not letting the world's economic woes discourage it from making strategic investments. We believe Intel hopes to dominate analog and RF applications the way it has dominated the microprocessor industry for many years.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1007/164001.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Tom R. Halfhill - Senior Editor
{10/07/2002}
Tensilica has licensed IBM's CoreConnect
on-chip bus and is introducing a bus bridge for its Xtensa V customizable
processor. The bridge allows system-on-chip (SoC) developers to
integrate CoreConnect-compatible intellectual property (IP) with
Xtensa processor cores.
The Xtensa architecture has a configurable processor bus that can
be 32, 64, or 128 bits wide, according to the requirements of the
customer's design. It doesn't directly support any industry-standard
bus interfaces, so developers usually create their own interface
from scratch or use gaskets to adapt the bus to a de facto standard
such as AMBA. The new CoreConnect bridge can eliminate that effort
and make it easier to attach readily available peripheral IP to
an Xtensa processor. Developers can also use the CoreConnect bus
to link together several Xtensa cores in a multiprocessor SoC.
The CoreConnect license reflects Tensilica's growing relationship
with IBM. Earlier this year, Tensilica became the first Platinum
member of IBM's Blue Logic IP Collaboration Program, an association
of IP vendors. IBM has qualified the Xtensa core in its Blue Logic
ASIC design program for fabrication in IBM Microelectronics' 0.13-
and 0.18-micron CMOS processes. The Platinum rating means IBM and
Tensilica have at least one customer design in volume production
using the Xtensa core.
IBM announced CoreConnect in 1999 after using a proprietary version
of the bus in ASIC designs for about two years (see MPR 7/12/99-03,
"PowerPC 405GP Has CoreConnect Bus"). To push CoreConnect as an
informal industry standard, IBM generalized the bus architecture
for external use, made it more CPU independent, and began freely
licensing it to other companies. Bridges are available to adapt
CoreConnect to other on-chip buses, including AMBA and ZSP. There
are currently 38 CoreConnect licensees, including Analog Devices,
Cadence, Ericsson, Lexra, LSI Logic, Lucent, Mentor Graphics, Nokia,
Siemens, and Synopsys. There are no up-front licensing fees or royalties
for using CoreConnect.
To find out more about Microprocessor Report, please visit:
www.mdronline.com.
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