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Issue #156
-- 11/25/2002
Editor: Tom R. Halfhill
In this issue:
Peter Glaskowsky - Editor-in-Chief
{11/25/2002}
Each year, Microprocessor Report’s analysts and editorial board work together to select the very best microprocessors on the market and the emerging technology of the greatest importance to our industry. We look at all the products available during the calendar year, define categories that give us a good selection of competitors, announce our nominees, and finally—at a special dinner event early the following year—announce the winners of the Microprocessor Report Analysts’ Choice Awards.
All these awards are associated with year-in-review articles that will appear in MPR shortly after the awards ceremony. The articles drive the awards process: if we need an article to explain what’s been going on in a market segment during the course of the year, we believe the best example of a processor in that segment deserves an award. We’ll publish our list of nominees soon, but I’d like to go through the categories now. We’ve chosen ten categories this year, using as a basis market and technical issues. Each category reflects a particularly competitive segment of the overall microprocessor market.
PC processors in 2002 represent a broad range of design optimizations. There are chips designed to deliver maximum performance, low power consumption, excellent price/performance, and the lowest possible cost. Deciding which of these characteristics means the most in today’s PC industry is tantamount to picking a winner. Intel’s Pentium 4 won this award last year, but the market has changed since then. Is Pentium 4 the best product for the market today? Our PC-processor analyst, Kevin Krewell, will explain our thinking in his PC-market year-in-review article in January.
Server processors generally focus on maximum performance for server applications, such as database queries and Web-page delivery over the Internet. Even so, server processors reflect a variety of design goals. Furthermore, server CPUs are the last bastion of the old RISC-versus-CISC debate, now with additional competition from EPIC products. IBM’s Power4 won this award for 2001, but some significant new products have been introduced since then. Kevin also covers this area, so look forward to his analysis after the awards are announced.
High-performance embedded systems support the greatest amount of differentiation among high-volume commercial microprocessors. There are RISC and CISC cores, SIMD and VLIW math accelerators, and instruction sets galore. A year ago, we gave a joint award to Motorola’s MPC 7455 and Broadcom’s BCM1250, but the competition will be even more intense this year. Picking a winner in this area won’t be easy, but under the guidance of Markus Levy, MPR’s primary analyst for this segment, we’ll sort it all out for you.
Low-power embedded applications put the greatest emphasis on efficient circuit design. In picking a winner among low-power embedded CPUs, we have to consider issues such as leakage current that simply aren’t an issue in our other categories. In-Stat/MDR principal analyst Max Baron covers this topic area for us, and he’ll explain our thinking behind this year’s award.
Max is also our primary analyst for extreme processors, an umbrella term I coined for CPUs that deliver extraordinary levels of performance for application-specific processing. We’re not giving an Analysts’ Choice award for DSPs this year, in part because we believe that, during 2002, extreme processors have made more interesting progress.
Tom Halfhill, back in the MPR fold following his sojourn with ARC Cores, will be analyzing intellectual property (IP) core offerings for 2002 and managing the associated awards. Last year, we considered the 20Kc core from MIPS the best of these items; this year will likely be different. Tom has an excellent understanding of these products, and we’re all looking forward to his analysis of them.
For 2002, we’ll be doing a year-in-review article and an Analysts’ Choice award for graphics processors. Last year, we gave the nod to the combination of Intel’s Pentium III and Nvidia’s XGU/MCPX chip set, the basis of Microsoft’s Xbox, as the best 3D-gaming platform. This year, we’ll be looking at discrete PC-graphics chips because, for the first time ever, there are several truly programmable 3D-rendering engines to compare and evaluate. With graphics processors—GPUs—now rivaling CPUs for complexity and manufacturing cost, the importance of these chips to system designers and end users has never been greater.
I’ll also be reviewing the related markets for network and security processors, which, more than any other type of CPU, reflect the trend toward application-specific processor design. The chips we’ll consider this year will be more than four times faster than the fastest examples from 2001—an impressive speedup. We’ll have awards in both these categories, as we did last year when IBM’s PowerNP NP4GS3 and Corrent’s CR7020 took home the honors.
The Microprocessor Report Technology Award is the one exception to our usual rule. This award could well be given to a technology not yet in commercial use. In past years, we’ve given this award to products that were announced but not yet shipping, such as IBM’s Power 4, as well as to scientific research projects like extreme ultraviolet (EUV) lithography, which one day will become crucial to microprocessor designers. Last year, the Technology Award went to Intel’s Hyper-Threading technology, because of its important contributions to the company’s current products as well as its potential for the future. I look forward to passing along the combined insights of our analyst team and editorial board on this subject.
Although the Analysts’ Choice awards provide a certain amount of excitement, the real value to you—our readers, our customers—comes from our analysis of the underlying issues that make one product or technology more important than others. I would appreciate whatever guidance you can offer in evaluating the nominees in each of these categories. Just drop me an email, and I’ll make sure it gets distributed to the rest of the analyst team.
To find out more about Microprocessor Report, please visit: www.mdronline.com.
Markus Levy - Senior Editor
{11/25/2002}
As the megahertz race continues, processor vendors continue to announce faster products. Despite the enormous performance potential of these processors, however, memory access presents the biggest bottleneck to unleashing this performance. Many ways exist to ameliorate the memory bottleneck, including out-of-order execution, larger on-chip caches, multiple pending bus transactions, hardware- or software-controlled prefetch mechanisms, nonblocking caches, and, obviously, faster memory.
Hardware-based multithreading (HMT) is another means for reducing the impact of the memory bottleneck. (This article contains a sidebar on multithreading.) Lexra’s LX4580 is the most recent processor added to the list of general-purpose embedded processors having simultaneous multithreading.
The first processor core coming from the MIPS-compliant Lexra is the LX4580; the company will use this core to build a family of products. The synthesizable LX4580 runs at 500MHz; the high clock frequency is in part the result of the even-issue rule’s elimination of the execution and memory bypass critical paths. The LX4580 architecture permits four active threads and hence includes four copies of various processor resources, including four sets of translation lookaside buffers in the MMU. Within the LX4580, when the processor is running a four-threaded application without cache misses, each thread will issue a new instruction every four clocks, in round-robin fashion. If a thread experiences a cache miss, it passes its turn to the next sequential thread. This thread sequencing continues until the cache miss is resolved.
Not all applications can be threaded. Initially, Lexra is focusing its marketing muscle on such “high-touch” applications as enterprise servers, security, storage networking, and edge-services infrastructures. High touch is also an area that companies such as Broadcom and PMC-Sierra are targeting with their respective BCM1400 and RM9000x2 products. The verdict is still out as to which approach delivers better performance—the traditional RISC with high-performance I/O or the multithreaded processor. HMT processors should deliver better throughput—but with longer latency than the highly pipelined and superscalar cores. On the other hand, a single-threaded processor with a nonblocking cache can overlap misses when sufficient instruction-level parallelism exists.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1125/164703.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Max Baron - Principal Analyst
{11/25/2002}
At In-Stat/MDR’s Microprocessor Forum 2002 NEC unveiled details of the company’s new massively parallel architecture, a dynamically reconfigurable processor (DRP). The new architecture can be used as a network processor or as a DSP engine in applications requiring high performance. The new architecture can execute both DSP and network processing workloads and its 512-processor elements can switch interconnections in one cycle. The architecture supports configurations of fall-through logic pipe-stages.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1125/164704.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Max Baron - Principal Analyst
{11/25/2002}
NeoMagic Corporation announced its fifth multimedia-focused system on a chip (SoC), the MiMagic 5. NeoMagic is targeting audio/video-rich markets such as multimedia messaging services (MMS), smartphones, mediaphones, personal digital assistants (PDA), wireless PDAs, and personal audio/video players. Billed as an applications processor, the MiMagic 5 is meant to run application programs rather than perform baseband processing for wireless and cellular communications.
MiMagic 5 offers a generous set of serial and general-purpose interface peripherals; support for USB 1.1 host and devices; timer-counters; an interrupt controller; output for LEDs; and interfaces for Compact Flash, PC card, secure digital (SD) card, and MultiMediaCard.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1125/164705.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Max Baron - Principal Analyst
{11/25/2002}
At In-Stat/MDR’s Microprocessor Forum 2002 Tensilica unveiled details of the company’s next-generation Xtensa ISA, a VLIW with flexible-length instruction extensions (FLIX). The new architecture targets performance-intensive systems on a chip (SoC) for applications in communications, multimedia, and network processing.
Continuing Tensilica’s existing approach, the new architecture can modelessly execute instructions in three formats, the new 64-bit VLIW format and the legacy Xtensa formats of 16 and 24 bits.
Using the new VLIW definitions, Conexant’s has built an engine designed to deliver high performance for media-rich workloads, modems, and wireless applications. Conexant’s engine comprises of three units: a load/store unit; a MAC processor that can operate on both real and complex data; and an auxiliary ALU that can also perform shifts and load/store operations.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1125/164706.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Max Baron - Principal Analyst
{11/18/2002}
Many recently introduced DSP architectures have delivered workload-optimized performance by using massively parallel processing at lower frequencies. The architects at Sandbridge, however, decided to adhere to multiprocessor configurations and—in order to extract performance—opt for operation at higher frequencies. Sandbridge has optimized the architecture of its basic core to consume minimal power. The multithreaded processor architecture executes DSP, control, and Java code in a single compound instruction.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1118/164601.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Markus Levy - Senior Editor
{11/18/2002}
Toshiba announced the first of the chips in its TX99 family, the TMPR9961, last month at Microprocessor Forum 2002. Toshiba has based the TX99 upon an enhanced MIPS64 core, a derivative of the 20Kc, that includes a level 2 cache and a variety of multimedia-related peripherals. Toshiba plans to take the core and develop chips targeted at the consumer market. Key features of the new chip, built in a 90nm process, include an 800MHz TX99 core, 32MB of embedded DRAM (eDRAM) for graphics, USB and FireWire links, an MPEG demultiplexer, and a graphics controller.
The Amethyst core has four-way set-associative 256K level 2 cache. The processor uses a 6.4GB/sec (at 400MHz) point-to-point demultiplexed bus with separate 64-bit inbound and outbound data buses to fill the level 2 cache. The TMPR9961’s peripherals are tied together with a bus hierarchy that includes an AMBA bus structure and a 200MHz crossbar switch using point-to-point connections. The chip’s embedded DRAM is directly connected to the integrated 2D/3D graphics controller through a 150MHz, 256-bit-wide interface.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1118/164603.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Markus Levy - Senior Editor
{11/18/2002}
Motorola has finally moved its PowerQUICC II products to a 0.13-micron process with the introduction of three new members of the family—the MPC8270, MPC8275, and MPC8280. The process shrink provides an approximate 50% increase in operating frequency, with a corresponding 20% decrease in power. The PowerQUICC II processors include both an embedded PowerPC 603e G2 core and a RISC-based communications processor module that offloads peripheral tasks from the embedded core and provides support for multiple communications protocols. The feature set of the new products is basically the same as that of existing PowerQUICC II products, with a few notable exceptions, including support for USB 1.1 and support for 31 PHYs in internal-rate mode.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1118/164604.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Peter Glaskowsky - Editor-in-Chief
{11/11/2002}
What if you could design a new x86 microprocessor core specifically for embedded systems? You would want a synthesizable design with configuration options to support system-on-chip applications, efficient low-power operation, and a gate count competitive with other synthesizable embedded cores. You wouldn't emphasize superscalar design, speculative execution, or the highest possible clock speed, as PC-processor vendors do.
These are the goals of startup MemoryLogix, which announced at Microprocessor Forum 2002 that it is developing such a core, the MLX1. MemoryLogix co-founder Peter Song, a former Microprocessor Report analyst, presented the details of the new core, which should be available for licensing by 3Q03.
MemoryLogix hopes to compete on nearly even terms in cost and performance with current embedded cores such as the ARM10, but with the added advantages of multithreaded execution and compatibility with the x86 instruction set.
As the market for embedded processors grows, new niches are created that can support new processor architectures. It's also possible that some of these niches can support a new approach to one of the market's oldest architectures. A purpose-built x86 core that can compete directly with the current market leaders will be of great interest to embedded-system designers. It's up to MemoryLogix to turn this interest into a business.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1111/164502.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Tom R. Halfhill - Senior Editor
{11/11/2002}
IBM is sampling the PowerPC 405EP, the newest member of its popular 405 family of SoCs. It's intended for small routers, wireless LAN access points, broadband modems, and other network-edge products, although it's also suitable for a variety of embedded systems.
Notable additions to the 405EP over the existing 405GP are a second Ethernet MAC, five general-purpose timers, and eight more general-purpose I/O pins. Notable subtractions are CodePack decompression, the 32-bit peripheral bus, external bus mastering, and support for synchronous PCI. Furthermore, the 405EP supports only three external PCI masters, vs. six in the 405GP.
The 405EP costs about 29% less than the 405GP and consumes 50% less power. It's a good deal for customers who don't need CodePack or 32-bit peripherals and could put the second Ethernet MAC to good use.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1111/164503.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Markus Levy - Senior Editor
{11/11/2002}
The MIPS-compatible NEC VR5500 will soon be built in a 0.13-micron node with a 0.095-micron gate length to achieve clock rates from 800MHz to 1GHz, providing a substantial performance jump over the currently available version. NEC demonstrated this 800MHz version at Microprocessor Forum 2002.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1111/164504.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Peter Glaskowsky - Editor-in-Chief
{11/04/2002}
Even the fastest networks can now be secured against digital eavesdropping. Intel’s new IXP2850 network processor (NPU) adds a full-speed cryptography engine to the company’s current IXP2800, making it not only the fastest NPU with integrated security processing but also the fastest security chip of any kind.
The IXP2850, like the IXP2800, is a half-duplex NPU, meaning two chips are required to handle bidirectional 10Gb/s packet processing. The new NPU is designed to support secure Internet Protocol (IPSec) operations and does not include a public-key cryptography accelerator. The IPSec protocol is used in virtual private network (VPN) applications.
The IXP2850 will commonly be used in equipment that carries a mix of encrypted and nonencrypted traffic, such as enterprise and service-provider routers, switches for Web server farms, and storage systems. An NPU as fast as the IXP2850 will rarely be kept completely busy handling encrypted traffic from the public Internet. The chip will give equipment makers a great deal of flexibility—and some interesting challenges—in making full use of its capabilities.
Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2002/1104/164401.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.
Max Baron - Principal Analyst
{11/04/2002}
Capable of delivering performance in the
GOPS range, microprocessors for data-intensive applications have
been arriving in all sizes and shapes, some from large semiconductor
design houses, some from hopeful startups, and some still hot from
their university ovens. Relying on instructions and data locality,
classical on-chip memory hierarchies have been good for general-purpose
processors but less useful in dealing with data streams that exhibit
poor locality. To mitigate problems of memory bandwidth, engineers
at Micron turned the classical design inside out: instead of placing
a processor core on chip and attaching memory to it, Micron architects
incorporated a large block of memory on chip and connected to it
a massive computer. Yukon, a prototype chip capable of ideally executing
51.2 billion 8-bit operations per second was unveiled by Micron
at MPR’s annual 2002 Microprocessor Forum. Micron’s target applications
for the new chip are image and video processing; speech compression
and decompression; and data mining.
Microprocessor Report readers can access the full story here:
www.mdronline.com/mpr/h/2002/1104/164402.html. To find out more
about Microprocessor Report, please visit:
www.mdronline.com.
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