Embedded Microprocessor Watch

Issue #160 -- 03/31/2003

Editor: Tom R. Halfhill

In this issue:

• IBM Opens Up PowerPC Licensing
• Does Intel Innovate?
• Moore, Moore, and More at ISSCC
• Octera Throws a Javalon
• Five Chips From TI—Or, Is It Six?
• ZSP500 and Jazz Play Different Beats
• The Sand in Manitoba
• Motorola Processor Cools Down
• MIPS Embraces Configurable Technology
• Chartered Seeks Lucrative Customers

IBM Opens Up PowerPC Licensing
Tom R. Halfhill - Senior Editor  {03/31/2003}

IBM’s long-awaited decision to openly license PowerPC cores will offer formidable new competition for ARM, MIPS Technologies, and other vendors of 32-bit microprocessor cores. It’s not just that PowerPC is a popular, scalable architecture with a wealth of development tools and software. IBM’s marketing muscle will give the company an instant presence in the intellectual property (IP) marketplace, and its rocklike stability makes it a safe haven for nervous customers in tough times.

Although IBM Microelectronics has been licensing PowerPC cores to ASIC and SoC developers for years, customers had to manufacture the chips in IBM’s fabs, which are famously competent but sometimes prohibitively expensive. Until now, the only alternative for developers was to implement their chip design in a Xilinx FPGA, thanks to a special licensing arrangement that allows Xilinx to integrate PowerPC 405 processor cores into programmable logic devices. Under IBM’s new open-licensing program, ASIC and SoC developers can take a PowerPC core to any independent foundry—such as TSMC, UMC, or Chartered—for manufacturing. This can save money and give developers more flexibility to port the cores to different fabrication processes.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0331/171302.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Does Intel Innovate?
Peter Glaskowsky - Editor-in-Chief  {03/31/2003}

In speeches they gave in early March, AMD chairman Jerry Sanders and CEO Hector Ruiz took Intel to task for failing to deliver "true innovation" and for holding back innovation by the rest of the PC industry. These claims centered on Intel’s dominant role in developing new PC processor and platform technology. Sanders and Ruiz seem to believe the PC industry would be making faster progress if Intel weren’t quite so powerful.

I think it’s clear that Intel is a highly innovative company. There’s no doubt Intel has contributed many important technologies to the PC industry over the years. Without Intel’s work, the PC would be much less powerful and flexible—and much more expensive.

But Intel’s efforts aren’t entirely beneficial. I believe Intel often takes too narrow a view of market needs and therefore overlooks opportunities to make its innovations more valuable. For example, when Intel realized the PCI bus was becoming a bottleneck for system performance because of the bandwidth PCI graphics cards consumed, Intel solved the problem by introducing the AGP interface.

Intel failed to recognize, however, that graphics cards are just one of several demanding peripherals on the PC platform. Instead of developing AGP solely for graphics, Intel should have created a more flexible high-performance interface that could be used for graphics, storage controllers, and network interfaces. Intel’s failure to solve the greater problem delayed development of high-speed peripheral interfaces for the PC platform, delays lasting to the present day. Even now, Intel’s mainstream PC chip sets offer nothing better than the old standard 32-bit, 33MHz PCI bus for expansion slots. This baseline PCI implementation became a bottleneck for many peripherals almost two years ago, and, for most customers, the solution—PCI Express—is still a year away.

InfiniBand was Intel’s first attempt to truly replace PCI, but it had the same problem AGP had: it was too specifically adapted to storage and networking to be useful as a general-purpose expansion bus. InfiniBand survives, but only for limited applications.

In some cases, Intel refuses to accept the importance of work done by other developers. Intel was very slow to pick up on PCI-X, which became necessary because of Intel’s misdirected work on AGP and InfiniBand. Intel should have introduced 64-bit PCI, followed by PCI-X, for its mainstream systems starting in 2000, but the company chose to use these faster buses in workstations and server systems only.

Sometimes, Intel refuses to license its technology to other companies that would use it to benefit PC buyers. Intel is famously reluctant to license its processor front-side buses, especially to competitors. I can’t fault Intel for this policy, however; its primary duty is to its shareholders. Although an open licensing program might help the PC industry, it would probably hurt Intel. Intel has no obligation to adopt self-destructive policies, no matter who benefits. Intel is entitled to control its proprietary technology and to profit from it.

Today, Intel offers some of the best processors, core-logic chip sets, and peripheral chips on the market. In other areas, such as 802.11 wireless networking, Intel is lagging behind other companies. It will surely invest what is needed to catch up with other 802.11 developers; it is already participating in most of the 802.11 subcommittees—and leading some of them.

Intel is extending its influence beyond the PC market into the cell phone and consumer-electronics markets, but it is not in a position to dominate these markets as it has dominated the PC-processor business. I hope the company learns from its mistakes and adopts a more thoughtful and cooperative attitude. If it tries to force stopgap solutions and half measures into consumer products, as it has done in PCs, it is likely to find its efforts at innovation, along with its products, rejected by the OEM community.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0331/171303.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Moore, Moore, and More at ISSCC
Peter Glaskowsky - Editor-in-Chief  {03/24/2003}

At the International Solid State Circuits Conference (ISSCC 2003), Gordon Moore reaffirmed the relevance of his namesake law, Chuck Moore of the University of Texas at Austin revealed an intriguing new processor architecture, and—oh, yes—there were papers on many interesting circuit designs. ISSCC has grown well beyond its roots as a showcase for innovative solid-state circuits to cover architectural theory, commercial implementations, and roadmaps for related technologies.

Among the actual circuits disclosed at ISSCC 2003 were high-resolution CCD and CMOS imagers for motion-picture cameras, a Z-80 on a glass substrate, and several 90nm designs from Intel, including a 10GHz RISC core, a 5GHz FPU, and a 5GHz clock-distribution scheme with less than 10ps of skew, meant for a commercial x86 microprocessor.

Two pure architecture papers added some variety to the transistor-intensive ISSCC program this year. One, from Princeton University, with contributions by Agere and IBM, covered a cache-optimization technique called timekeeping. Timekeeping involves keeping track of the time intervals associated with cache operations like allocation, access, and eviction.

Perhaps the most important presentation at ISSCC, in its potential for long-term influence on the computer industry, was given by Chuck Moore, formerly chief engineer on IBM’s Power4 processor and now a research fellow at UT-Austin. Moore is part of a team at UT-Austin and IBM’s Austin Research Lab working on the TRIPS (Tera-op Reliable Intelligently adaptive Processing System) project, an effort to develop a new family of grid processor architectures (GPA) designed to permit dramatically higher ALU utilization on all types of code. Early simulations show a potential for average instructions-per-cycle values as high as 11 across SPEC2000 and Mediabench benchmarks.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0324/171201.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Octera Throws a Javalon
Tom R. Halfhill - Senior Editor  {03/17/2003}

Only a few years ago, engineers despaired of using Java for real-time embedded applications because of its obesity and nondeterministic behavior. Java seemed more suitable for desktop PCs and servers that could satisfy its appetite for megabytes and megahertz. Yet, from the very beginning, Sun had conceived Java as a programming language and virtual platform for an embedded application—interactive TV set-top boxes. Perhaps it is inevitable that Java is returning to its roots.

Now some companies are pushing Java into a very different frontier: deeply embedded applications that demand hard real-time performance. Examples might include motor controllers, industrial machinery, smartcards, automotive telematics, and other mundane systems that aren’t as sexy as Web-browsing, game-playing cell phones but nevertheless keep the world turning. To address those applications, San Diego–based Octera is introducing Javalon-1, a synthesizable microprocessor core that natively executes Java bytecode instructions. Javalon-1 is the first member of a small family of cores that will have minor variations on the same basic design. Chip designers can use Javalon-1 as the basis for a self-sufficient microcontroller or as a slave to another microprocessor core on an SoC or ASIC.

Javalon-1’s memory requirements are unusually low (about 5K of firmware, not counting application memory). It doesn’t need a Java virtual machine (JVM), a Java bytecode interpreter, or a just-in-time (JIT) bytecode compiler, because it natively executes Java bytecode instructions in hardware or software. It doesn’t use a garbage collector to manage memory, so it’s deterministic and has relatively low interrupt latencies (about 100 clock cycles, worst-case). And it’s suitable for small embedded systems because it’s compact (about 25,000 logic gates). Octera is wrapping up the design work now and plans to begin licensing Javalon-1 in 3Q03.

What’s the catch? Javalon-1 isn’t officially a Java processor because it doesn’t fully comply with Sun’s Java specifications. In general, it follows the Java 2 Micro Edition (J2ME) and Connected Limited Device Configuration (CLDC) guidelines, but it makes several compromises to achieve its fast interrupt response, efficient memory usage, and low gate count. Javalon-1 is more accurately described as a Java-like processor or as a processor that executes Java bytecodes without fully supporting a Sun-standard Java platform. Some of Octera’s trade-offs are sure to be controversial.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0317/171102.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Five Chips From TI—Or, Is It Six?
Max Baron - Principal Analyst  {03/17/2003}

The race for the cell phone is shifting into high gear. Large semiconductor companies have introduced chips that can execute applications in handsets. Now, they are launching faster, higher-integration chips that add DSP and hardwired accelerators to execute digital baseband functions.

Texas Instruments, a leading supplier of chip sets for cellular phones, recently introduced six processors, all announced before the 3GSM Conference in February. Three of the chips—OMAP1610, OMAP1611, and OMAP1612—provide generic digital baseband and application processing resources. Two chips—OMAP730 and OMAP732—have dedicated GSM/GPRS digital baseband modem support and resources for processing application programs. The final chip, TBB4105, not yet individually introduced by a specific press release, is a complex Swiss Army Knife–style engine to support WCDMA and GSM/GPRS plus applications; based on the same core as the OMAP1610, the TBB4105 is part of a TI cell-phone chip set.

Special attention has been paid to security, a first claimed by TI. Security is an important differentiator in cellular communications, as it affects voice, multimedia, and data. TI has included a secure boot loader, 48KB of secure ROM, 16KB of secure RAM, several hardware accelerators supporting security standards, and a random-number generator.

TI and STMicroelectronics have agreed to propose an abstraction layer for adoption as a standard. The proposed abstraction layer is the Open Mobile Application Processor Interface (OMAPI) for applications processors targeting 2.5G and 3G mobile phones, PDAs, and other portable and multimedia products. TI has stated that its OMAP161x and OMAP73x chips are OMAPI compliant.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0317/171103.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

ZSP500 and Jazz Play Different Beats
Markus Levy - Senior Editor  {03/17/2003}

The mobile phone market is hot, and every company that makes a DSP or other processor wants a piece of the action. Reading the product literature, you’ll usually find marketing blurbs claiming each company’s devices or cores are perfectly suited for the mobile environment, although we suspect few will ever succeed. Two cores that embody this aspiration are LSI Logic’s ZSP500 and Improv Systems’ Jazz, although the cores are so dissimilar, we find it hard to believe both could target similar markets. In fact, both LSI and Improv have insisted that comparing the two architectures is a big stretch. We therefore thought it would be interesting to examine some features of these cores and their performance and draw our own conclusions about the cores’ likelihood of finding homes within mobile phones.

The ZSP500, the first core derived from LSI Logic’s new ZSP G2 architecture, is targeted at consumer multimedia and mobile applications. This application area is where the comparison overlaps the noticeably different architecture of Improv Systems’ Jazz DSP, especially Improv’s Crescendo product, which specifically targets Internet appliances and 3G wireless devices. The ZSP500 is based on a four-issue superscalar architecture with an eight-stage interlocked pipeline and a 16-bit fixed-point datapath. Improv Systems' Jazz DSP Processor is a VLIW embedded-processor architecture with a two-stage instruction pipeline and a mix of heterogeneous, single-cycle execution, user-designed computer units.

EEMBC scores for the Jazz DSP, derived from optimized versions of the EEMBC benchmarks, revealed that the performance of this DSP was almost too good to be true. But performance isn't the only important metric. When we compare the optimized results for the ZSP500 and the Jazz XT, we find that the Jazz XT sports large performance gains over the ZSP500 for the Telecom benchmarks, but consuming several times the code memory space in the process.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0317/171104.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

The Sand in Manitoba
Max Baron - Principal Analyst  {03/10/2003}

Code-named Manitoba, the PXA800F, Intel's "wireless-Internet-on-a-chip" for cell phones targets data-capable "mainstream" phones in the 2.5G and 3G categories, forecast to become a hefty slice of the total handset market. Intel's targeted cellular phone is positioned between the 2G speech-only device and the 2.5G/3G smart phone that can deliver PDA-like functionality.

Intel's new chip combines a compute-intensive block almost identical to the one in Intel chips that target the PDA; a communications block strengthened by a programmable DSP; and accelerators, peripherals, and power management. Intel claims it already has fully functional PXA800F samples, some of them in the hands of prospective customers.

The company has stated it expects cell phones using PXA800F to be offered this year or early next year.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0310/171001.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Motorola Processor Cools Down
Markus Levy - Senior Editor  {03/10/2003}

Motorola is playing a game of leapfrog with itself. In the embedded processor market, the MPC7455 is the only device to ship at the 1GHz mark. While other vendors, such as Broadcom and PMC-Sierra, haven't yet reached mass production with gigahertz devices, Motorola just announced that it has surpassed itself, by sampling the 1.3GHz MPC7447 and MPC7457. The new 74x7 devices have the same G4 microarchitecture as the 74x5 devices, the only difference being the doubling of the L2 cache, from 256K to 512K, but this, along with an increased clock speed, has had an obvious benefit on the processor's performance. In addition, the process change to 0.18 micron has made a significant difference on die size and power consumption.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0310/171003.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

MIPS Embraces Configurable Technology
Tom R. Halfhill - Senior Editor  {03/03/2003}

MIPS Technologies is the latest company to endorse the concept of configurable microprocessor cores. At Embedded Processor Forum 2002, MIPS introduced the M4K Pro synthesizable processor, which implements a revision of the MIPS32 instruction-set architecture (ISA). Along with that revision, MIPS opened the door for customers to add application-specific instructions to the M4K. More recently, MIPS announced that all soft processors in the Pro Series are user configurable, thanks to a technology MIPS refers to as CorExtend. Initial Pro Series cores, in addition to the M4K, are the 4KSd, 4KEp, 4KEm, and 4KEc.

The first obvious question is whether CorExtend matches the more-mature configurable-processor technology from ARC and Tensilica. The short answer is no. At this time, MIPS Pro Series cores have fewer configurable options than do the ARCtangent-A5 or Xtensa V cores. Furthermore, ARC and Tensilica offer better tool-chain integration.

Although MIPS Pro Series cores are less broadly configurable than the ARCtangent and Xtensa cores, they do have the most important feature: an extendable instruction set. This allows designers to leverage the familiar 80/20 rule, which holds that 20% of a program usually does 80% of the work. Software programmers use profiling tools to identify those “hot spots,” then optimize the critical algorithms or inner loops with tighter code or assembly language. Hardware designers can do the same thing by creating custom instructions that execute the critical functions in logic. Doing this can often boost performance by an order of magnitude or more. In other words, a little configurability goes a long way.

The big selling point for MIPS is that customers can now license a configurable microprocessor core without having to adopt an alien CPU architecture. In the market for 32-bit embedded processor cores, only ARM is more pervasive than MIPS, and ARM hasn’t yet embraced configurable technology. Although ARC and Tensilica have very respectable CPU architectures from a technical standpoint, they are less “standard” than is the MIPS architecture, one of the seminal RISC architectures developed during the 1980s. Hundreds of universities worldwide use the MIPS architecture as a teaching tool, and it’s strongly supported by third-party development tools and peripheral intellectual property. The Pro Series cores with CorExtend are backward compatible with this architecture.

It has always been possible for MIPS licensees to extend the MIPS instruction set, but doing so formerly required an architectural license instead of the more common (and less expensive) core license. It has also been possible for MIPS licensees to add new instructions and local state registers by attaching function blocks to the coprocessor interface, a feature of some MIPS cores. However, even MIPS now acknowledges that the rarely used coprocessor interface is not the ideal solution. With CorExtend, customers don’t need an architectural license to add a few application-specific instructions to a Pro Series core.

CorExtend is proof that configurable-processor technology is coming of age. ARC and Tensilica have blazed the trail, and now the technology is attracting the attention of more-established companies like MIPS. In time, ARM will almost certainly follow. The rewards for making hardware as malleable as software are becoming too great to ignore.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0303/170901.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Chartered Seeks Lucrative Customers
Tom R. Halfhill - Senior Editor  {03/03/2003}

Reeling from what it describes as the sharpest market decline in the history of the industry, Chartered Semiconductor plans to close its oldest fab and refocus on customers that need advanced fabrication processes. The Singapore-based company’s goal is to increase its fab capacity for 0.18-micron and smaller processes from 15% in 2002 to 50% by the end of 2004, without expanding total capacity.

Chartered’s net losses for the past two years total $801.1 million. To turn its business around, the company will close the oldest of its five fabs in Singapore by March 2004. That is the only Chartered fab still limited to making 150mm wafers; the company’s other four fabs produce 200mm wafers. Chartered was planning to begin pilot production of 300mm wafers at its newest Fab 7 in Singapore by 3Q03, but a recent deal with IBM to jointly develop new technology and share fab capacity is allowing Chartered to delay 300mm production until 3Q04. (See MPR 12/16/02-02, “IBM and Chartered Join Forces With Fabs.”)

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0303/170902.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.