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Issue #161 -- 04/28/2003
Editor: Tom R. Halfhill
In this issue:
Markus Levy - Senior Editor {04/28/2003}
By personal computer standards, 720MHz is
ancient history. So is it such a big deal that TI’s TMS320C64x VLIW
DSP made it into the Guinness Book of World Records with a wimpy
720MHz part? Those of us not caught up in the mega- and gigahertz
hoopla appreciate the fact that clock rate is not the sole driver
of performance. I’ve always emphasized that performance is a parallel
design effort that balances clock rate and the number of operations
per clock. An analysis of TI’s C64x demonstrates that this commercially
available product family delivers on both aspects of the performance
metric.
The C64x has its roots in the TMS320C62x, the architecture that
introduced VLIW processing to the mainstream. The C62x and the C64x
have many similarities, such as the foundation of the architectures.
The primary elements of both modified VLIW DSPs are two mirror-image
banks of registers and eight functional units served by independent
datapaths. With these eight functional units, the C64x can theoretically
execute as many as eight instructions per cycle. On the other hand,
the C64x contains many enhancements over the C62x, some subtle and
some substantial. As we will demonstrate, the C64x derives a big
performance boost from these and other enhancements.
Microprocessor Report readers can access the full story here:
www.mdronline.com/mpr/h/2003/0428/171702.html. To find out more
about Microprocessor Report, please visit:
www.mdronline.com.
Peter Glaskowsky - Editor-in-Chief {04/28/2003}
I joined MDR seven years ago to cover PC
platform technology, an area that has experienced tremendous progress
over the years. In just the past three years, we’ve seen front-side
bus speeds—a critical constraint for processor performance—soar
from the 133MHz of Intel’s Pentium III to the 800MHz of the new
Pentium 4. That’s a 6:1 improvement, better than Moore’s Law would
predict. Memory bandwidth has increased comparably, with single
banks of 133MHz SDRAM giving way to the dual banks of DDR400 SDRAM
in today’s best desktop PCs.
Software development used to lead hardware development: each new
version of Windows and each new major application, such as DVD playback,
used to arrive before PCs were fast enough to take full advantage
of them. Today, the situation is reversed. Even low-cost PCs are
more than fast enough for the software they’re likely to run. Only
in a few niche markets, such as 3D games, are PCs strained to their
limits.
Peripherals have also lagged behind. The ATA hard-disk interface
is just twice as fast today than it was three years ago. The hard
disks themselves are improving at a similar rate, but they continue
to be a limiting factor for many kinds of software. The 100Mb/s
Fast Ethernet standard still accounts for almost all local-area
networks; Gigabit Ethernet has been slow to catch on.
During the next year, we’ll see several new technologies arrive
on our desktops that will help break these performance logjams and
open the market to new applications. The Serial ATA standard, for
example, will support a 150MB/s transfer rate, and this rate will
double again within two years. Serial ATA will make it easier for
end users to add another drive to their systems, and, with disk-array
technology, such an upgrade can boost performance as well as capacity.
PCI Express will remove another obstacle to end-user system expansion
by providing more than enough bandwidth for tomorrow’s high-performance
peripherals. The familiar PCI bus isn’t even fast enough for many
of today’s needs, so PCI Express is long overdue.
I/O coprocessing isn’t a new technology, but it’s one we’re likely
to see more of in mainstream systems. Graphics cards are coprocessors
already, doing tasks that were once the responsibility of the CPU.
I believe networking will be the next major role for coprocessors
in the PC. Running the TCP/IP stack for a Gigabit Ethernet link
can consume the equivalent of a 2GHz processor—or a $20 ASIC. That’s
a pretty easy choice to make. On the other hand, high-definition
video processing is only a temporary market for coprocessors. The
HDTV standard will be with us for many years, and CPUs will soon
be fast enough to handle HDTV for most users.
The transition to 64-bit desktops, however it takes place, will
impose new requirements on the PC platform. With 4G of DRAM available
at retail for less than $500, and with further price cuts inevitable,
we need to have PC motherboards with more memory slots than the
two or three that have become commonplace—at least at the high end
of the market. Similarly, now that multithreaded operating systems
and applications are commonplace, we should see a return to dual-processor
configurations for high-end desktops.
PC buyers have always responded well to technology transitions that
promise dramatic improvements in system capabilities, and software
developers have always come through with new ways to take advantage
of these capabilities. Today’s PCs are more than a match for yesterday’s
supercomputers. What will tomorrow’s PCs be like?
To find out more about Microprocessor Report, please visit:
www.mdronline.com.
Tom R. Halfhill - Senior Editor {04/21/2003}
Small is good if you’re a jockey, a designer
dog, or a microprocessor chip. Ubicom (meaning “ubiquitous communications”)
is a company that definitely thinks small when it designs packet
processors for wired and wireless systems.
Its latest NPU is the IP3023, which requires only about 50% as much
silicon and 10% as much memory as some competing chips.
Ubicom designed the IP3023 for wireless access points, wireless
LAN (WLAN) bridges, broadband modems, home routers, and other consumer
or enterprise products that operate near the edge of a network.
The company’s goal is to slash the bill of materials (BOM) for those
systems by offering an efficient packet processor that reduces or
eliminates the need for off-chip memory and protocol-specific I/O
chips.
The 32-bit IP3023 is the first implementation of Ubicom’s next-generation
processor architecture. Priced at only $12, it follows Ubicom’s
even more economical 8/16-bit IP2022 and IP2012 packet processors.
(See MPR 5/28/02-03, “Ubicom Breaks New NPU Ground.”) For $1 less
than the price of the IP2022 at introduction two years ago, the
IP3023 delivers many more features and an estimated 10 times more
performance.
Other packet processors based on MIPS or ARM cores have the advantage
of familiar architectures, even if, in Ubicom’s eyes, they are “obsolete”
RISC engines. However, the IP3023’s architecture is so RISC-like
and simple (only 39 instructions) that the learning curve for developers
isn’t too steep. And Ubicom provides I/O drivers to implement an
Ethernet media-access controller, 802.11 media-access controller,
USB, PCI/CardBus, PCMCIA, IDE, ISA, Utopia, GPSI, SPI, and UARTs
in software on the IP3023.
Microprocessor Report readers can access the full story here:
www.mdronline.com/mpr/h/2003/0421/171601.html. To find out more
about Microprocessor Report, please visit:
www.mdronline.com.
Markus Levy - Senior Editor {04/21/2003}
Hitachi Ltd. and Mitsubishi Electric officially
cast off their semiconductor businesses to the new joint venture
known as Renaissance Semiconductor for Advanced Solutions, or Renesas
Technology Corporation. The combined forces that constitute this
new business put Renesas in one of the top five positions for semiconductor
sales worldwide.
Microprocessor Report readers can access the full story here:
www.mdronline.com/mpr/h/2003/0421/171602.html. To find out more
about Microprocessor Report, please visit:
www.mdronline.com.
Markus Levy - Senior Editor {04/21/2003}
During the week of March 24, Motorola held
its annual Smart Network Developer Forum. More than 500 engineers
from among Motorola’s customer base attended the event. Besides
being generically informative, the top focus of SNDF was the demonstration
of working silicon for Motorola’s 833MHz MPC8560, better known as
the PowerQUICC III communications processor.
Microprocessor Report readers can access the full story here:
www.mdronline.com/mpr/h/2003/0421/171603.html. To find out more
about Microprocessor Report, please visit:
www.mdronline.com.
Max Baron - Principal Analyst {04/14/2003}
Intel covered all price points and all frequencies
that mattered with its Pentiums and Celerons for desktops and notepads.
It is applying the same strategy to processors for PDAs and cellular
phones. StrongARM, Intel’s springboard chip, is probably close to
the end of its life, but, during its relatively short existence,
it won the PocketPC PDA market.
On March 24, Intel announced three new processors for PDAs. The
company is adding two new chips to its PXA26x series: the PXA263,
a stacked processor-and-flash memory device for PDAs, and the pin-compatible
PXA260 processor, intended to help OEMs build and upgrade PDA designs
with reduced cost and development time. The third processor is the
PXA255, Intel’s replacement for the short-lived PXA250.
Microprocessor Report readers can access the full story here:
www.mdronline.com/mpr/h/2003/0414/171502.html. To find out more
about Microprocessor Report, please visit:
www.mdronline.com.
Markus Levy - Senior Editor {04/14/2003}
SandCraft has refocused its design efforts
onto processors that will service high-volume applications such
as medium-range routers, storage-area network systems, home gateways,
and printers. Although we have not yet seen industry-standard benchmark
scores, we believe SandCraft’s new SR71040B possesses the appropriate
architectural features to meet the performance demands of these
applications.
SandCraft implemented a variety of circuit modifications to the
SR71040B’s pipeline, stemming from extensive critical-path analysis
that resulted in a 50% clock-rate improvement. Furthermore, improvements
in the ALU, register files, and result buffer yielded an additional
40–50MHz.
Microprocessor Report readers can access the full story here:
www.mdronline.com/mpr/h/2003/0414/171503.html. To find out more
about Microprocessor Report, please visit:
www.mdronline.com.
Markus Levy - Senior Editor {04/07/2003}
In early 2002, MPR compared the ARM1020E
and ARM1026EJ-S processor cores, using modeling and EEMBC benchmarks
to study the effects of the microarchitectural differences between
the two cores. Although both the synthesizable ARM1026EJ-S and the
semicustom ARM1020E cores are members of the ARM10 family, their
microarchitectural differences are sufficiently significant that
each will display diverse performance characteristics. New data
provided by the certified EEMBC benchmark scores for the ARM1026EJ-S
confirmed our theoretical analysis related to the behavior of the
ARM processor core, especially when it is compared with the ARM1020E
and other processors, such as SuperH’s SH-4, IBM’s 405GPr, and Intrinsity’s
FastMIPS.
Microprocessor Report readers can access the full story here:
www.mdronline.com/mpr/h/2003/0407/171401.html. To find out more
about Microprocessor Report, please visit:
www.mdronline.com.
Max Baron - Principal Analyst {04/07/2003}
On March 17, in New Orleans, TI announced
a new OMAP processor–based PDA reference platform that can deliver
simultaneous wireless voice and data connectivity. Code-named WANDA
for Wireless Any Network Digital Assistant, the new design signals
that TI intends to take an active role in pursuing smart cell phones—a
market segment that until now it seems to have kept on the back
burner.
WANDA will be delivered at first with a port of Microsoft’s PocketPC
to help it capture sockets in the higher-priced PDA market. According
to TI, the WANDA concept design will be available in April, at which
time TI may publish an official reference block diagram.
Microprocessor Report readers can access the full story here:
www.mdronline.com/mpr/h/2003/0407/171402.html. To find out more
about Microprocessor Report, please visit:
www.mdronline.com.
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