Editor: Tom R. Halfhill  

In this issue:

MIPS Pipeline Favors Synthesizability
Markus Levy - Senior Editor  {06/30/2003}

At Embedded Processor Forum 2003, MIPS Technologies announced its MIPS32 synthesizable 24K microarchitecture. The primary design goal for this microarchitecture is to enable a worst-case operating frequency of 400–550MHz when a processor is fabricated in a 0.13-micron process. The resulting microarchitecture is a single-issue eight-stage pipeline with a balance of features that maintains one instruction per clock without compromising the primary frequency goals.

The 24K microarchitecture implements a decoupled fetch unit that uses dynamic branch prediction to fetch the predicted execution path into a six-entry instruction buffer. To ameliorate the timing issue, MIPS started the 24K pipeline with two instruction fetch stages to support a two-cycle access for compiled RAMs. The instruction cache, configurable in sizes of 16-, 32-, and 64KB, has a 64-bit read port that transfers two instructions per access to the fetch buffer. The I-cache can generate up to two outstanding misses.

The 24K microarchitectureincludes a configurable memory-management unit that implements a translation-lookaside buffer (TLB) or a fixed-mapping translation unit. The architecture of the TLB supports a multilevel structure that includes a four-entry fully associative instruction micro-TLB that uses a least-recently-used (LRU) replacement algorithm. The fixed-mapping scheme is a build-time synthesis option. Fixed mapping eliminates the need for the micro-TLB and main TLB, reducing MMU functionality to a few gates that are used to perform a predefined virtual-to-physical address mapping.

The 24K microarchitecture is the first 32-bit synthesizable MIPS microarchitecture that features dynamic branch prediction, a necessary function of the longer eight-stage pipeline. The branch predictor uses a 512-entry bimodal branch history table. A four-entry return prediction stack automatically stores return addresses whenever a subroutine-entry instruction is executed.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0630/172601.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Now This Is a Horse Race
Peter Glaskowsky - Editor-in-Chief  {06/30/2003}

On June 23, Apple announced new PowerMac G5 computers based on IBM’s PowerPC 970 processor, which debuted at Microprocessor Forum last October. Apple CEO Steve Jobs made a series of dramatic claims for the new machine: world’s first 64-bit personal computer, world’s fastest PC, world’s highest-frequency 64-bit processor, and world’s fastest front-side bus. To support these claims, Jobs announced the results of SPEC CPU2000 testing by independent test lab VeriTest and application-based testing performed by Apple.

Individually, these claims are highly questionable. Some are simply not true: there were 64-bit processors in several RISC-based Windows NT desktops in the mid-1990s. Some are overstated: published SPEC scores for the Pentium 4 and P4 Xeon comparison systems are considerably higher than those Apple reported. Some are irrelevant: Apple knows perfectly well that clock frequency per se is essentially meaningless.

Taken together, however, along with a proper understanding of the new G5 system architecture and Apple’s share of the PC market, these claims support a more favorable conclusion: Macs are once again fully competitive with Windows PCs in performance and have feature advantages that should help Apple expand its market. Not long ago, it appeared that the Windows PC had taken an insurmountable lead.

VIA, another independent PC platform developer, recently established its right to compete with Intel on the desktop. VIA is focused on the low end of the Windows and Linux business, but these days, that’s where the high-volume sales opportunities lie.

It was also taken for granted, until recently, that RISC-based servers were on the way out. Intel’s x86 chips would own the low end of the server space, its IA-64 processors would take over the high end, and between them they would squeeze out the competition. As if accepting an inevitable fate, competing server vendors announced plans to cease developing their proprietary architectures.

But they didn’t. Only Alpha development has effectively ceased. PA-RISC and MIPS server chips are on life support, but there is as much competition as ever. AMD is investing heavily in Opteron, and Sun has pledged to revitalize its SPARC architecture with Throughput Computing, a combination of chip multiprocessing and multithreading. IBM is in this picture too with its Power series of server processors.

Instead of watching the market dwindle to a single vendor with two architectures, we have five strong CPU vendors with seven architectures among them. Only Sun is eschewing the PC desktop space; indeed, Sun’s Throughput Computing initiative seems to suggest the company is devaluing its workstation business as well in favor of strengthening its servers.

Seven horses make a good horse race, and this one should become even more exciting over time. Each company is betting on a particular sequence of architectural advances. Intel has two-way simultaneous multithreading in its x86 chips and will use dual-core multiprocessing in Itanium. AMD has upgraded its x86 chips with 64-bit support, something Intel is rumored to be considering, and has put some thought (but little public comment) into multicore designs. IBM has multiprocessing and multithreading expertise, and Sun is moving in that direction even more quickly.

All these decisions will have a greater influence on the end-user experience than previous architectural advances like superpipelining and superscalar design. Those approaches delivered raw speed, but the next wave of processor technology will affect the way applications run, not just how fast they run. Programmers will change the way they develop software, end users will adapt to the new platforms and programs, and we at Microprocessor Report will try to explain it all.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

Tensilica’s Software Makes Hardware
Tom R. Halfhill - Senior Editor  {06/23/2003}

Since the dawn of computing, programmers have been writing software to suit the hardware. What choice did they have? Code is flexible; metal is not. Until now.

At Embedded Processor Forum 2003 last week, Tensilica unveiled an impressive addition to the tool chain for its Xtensa configurable-processor architecture. A new code-analysis and hardware-generation tool—so new it doesn’t have a catchy name—automatically creates processor extensions that accelerate critical functions in C/C++ source code. Custom extensions can include new instructions, registers, and function units. In minutes, the tool can evaluate thousands of possible extensions and sort them by performance (clock cycles) and efficiency (gate count). When a developer selects the optimal design for the target application, the tool automatically generates the extension in Tensilica’s proprietary hardware design language and integrates it with the Xtensa processor core, ready for logic synthesis.

In addition to creating processor extensions, the new tool links into Tensilica’s existing tool chain, which automatically generates a C/C++ compiler, assembler, debugger, cycle-accurate software simulator, and real-time operating system (RTOS)—all tailored for the customized processor. The compiler automatically uses the new custom instructions to accelerate the application program without modifying the original C source code. And when the tool ships next year, it will plug into the new Xtensa Xplorer integrated development environment (IDE) that Tensilica announced on June 16.

We are aware of no other configurable microprocessor or tool chain that approaches this level of design automation. The configurable processors from ARC International and MIPS Technologies allow developers to create custom extensions for accelerating software, and code-profiling tools help programmers identify the most critical routines and inner loops. However, someone must still write the VHDL or Verilog code for the custom extensions and integrate it with the processor core. To evaluate alternative implementations of an extension, developers must manually create the extensions and test them, one by one, in a cycle-accurate simulator. In most cases, developers must also modify the software-development tools before using a custom extension and write intrinsic functions to use the new instructions in their application code.

In less time than it takes for a single iteration of that labor-intensive process, a developer using Tensilica’s new system will be able to explore thousands of possible extensions, generate the optimal choice, modify all the software-development tools, and recompile the application with optimized instructions.

Tensilica’s new tool has the potential to dramatically change SoC development. Hardware/software partitioning—physically dividing an application between functions performed in logic and functions performed by code—has never been easier. It’s a significant step toward a unified design methodology that is application-centric, not hardware- or software-centric.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0623/172501.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

IBM Offers SoC Head Start
Peter Glaskowsky - Editor-in-Chief  {06/23/2003}

When we think of hard macros for custom chip design, we usually mean a block of logic, such as a microprocessor, that will be surrounded by application-specific logic. IBM has turned this definition inside out with the new Customizable Control Processor (CCP) design platform, announced at Embedded Processor Forum 2003. The CCP approach starts with a hardened and verified design for the common elements of a system-on-chip (SoC) design—the CPU along with standard peripherals and I/O interfaces—and reserves a portion of the chip and I/O pad ring for customer-defined logic.

In the first CCP offering, IBM has created a hard “superstructure,” including a 333MHz PowerPC 405 core, processor-bus and SDRAM controllers, and some general-purpose peripherals. What’s left is enough room for about one million logic gates plus 1Mb of SRAM, along with 108 available I/O pins. Customer logic is implemented in a standard-cell ASIC design flow.

Custom CCP chips will be suitable for moderately high-volume products—those above the maximum threshold for FPGAs (typically 10,000 to 100,000 units) but below the point where the added cost of a completely custom ASIC will be fully amortized. IBM may have found a good compromise between ASICs and standard products, but it remains to be seen what portion of the market can be satisfied with the particular combination of features, performance, and flexibility found in the CCP platform. IBM’s foundry service is generally regarded as a premium product—expensive, but sometimes worth the cost. The CCP approach may make IBM’s services more widely affordable and desirable.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0623/172502.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

New Magic in MiMagic 6
Max Baron - Principal Analyst  {06/17/2003}

On June 17, 2003, at In-Stat/MDR’s Embedded Processor Forum (EPF 2003), Sanjay Adkar, VP of Corporate Engineering, presented NeoMagic’s new chip, MiMagic 6. MiMagic 6 employs a new type of multimedia and graphics accelerator that may propel NeoMagic out front, ahead of many of its competitors.

NeoMagic’s new magic is an on-chip Associative Processing Array (APA). APA is a massively parallel multimedia accelerator that performs computations in content-addressable memory and can be programmed to execute a variety of logical and arithmetic operations.

NeoMagic will aim the chip at smart imaging- and video-intensive cellular phones, wireless PDAs, and multimedia PDAs.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0617/172401.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

ARM Grows More Thumbs
Markus Levy - Senior Editor  {06/17/2003}

This week at the Embedded Processor Forum, ARM’s Vladimir Vasekin presented the details of instruction extensions for the v6 architecture. The new extensions include 32-bit ARM instructions for improved data handling, but even more interesting is the birth of a new version of Thumb that supports 32-bit operation codes. The extensions are packaged in a similar manner to the E or J extensions and will be available in a new ARM11-based core that ARM will announce later this year.

To achieve the best (or almost the best) of both worlds—optimal performance and highest-density code—ARM has created a new Thumb instruction-set architecture (ISA), called Thumb-2 (T2). T2 combines the pre-existing Thumb instructions with a handful of new 16-bit instructions and an armful of 32-bit instructions. For example, ARM has included a 16-bit If-Then instruction that is used to predicate a sequence of one to four Thumb instructions. There are also new 32-bit instructions that are common to both the ARM and Thumb ISAs; the most useful of these instructions are bit-field modifiers. In addition, this article describes the way ARM took about 130 instructions from the existing v6 instruction set and instantiated them into T2. The ARM instructions that went into Thumb were selected on the basis of their popularity, lack of redundancy, usefulness, and ease of implementation.

Although we might expect an extra stage in the pipeline to handle the 32-bit T2 decoding, this issue could be resolved by using a prefetch unit that can present fully formed T2 instructions to the decode stage, regardless of the alignment. This article describes the circumstances under which the 32-bit Thumb instruction will spend one extra cycle in the decode stage.

The data suggests that T2 instructions have yielded a substantial performance improvement. Preliminary EEMBC results show that on average, benchmarks compiled for T2 come within 2% of the ARM results. This represents a 20% performance improvement over the current Thumb mode. Furthermore, when the code is optimized for space (versus performance), T2 code is considerably smaller than ARM code.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0617/172402.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

ARM Makes Bus Announcement
Markus Levy - Senior Editor  {06/17/2003}

The Advanced eXtensible Interface (AXI), introduced at the Embedded Processor Forum 2003, is the most recent progression of AMBA. Although AXI maintains all the signaling of AHB, it differs significantly from AHB, adding features such as register slicing, the ability to perform multiple outstanding transactions and out-of-order returns, and the use of a channel architecture.

AXI is a channel architecture that supports a protocol comprising four independent channels: address, read, write, and write response. To support higher operating frequencies, the channel architecture of AXI allows insertion of register slices on any of the channels. AXI also supports a single address for an entire burst transaction and can handle multiple outstanding transactions and out-of-order returns. These are excellent features for SoCs that have a mixture of fast and slow peripherals.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0617/172403.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Intel Maps Wireless Future
Tom R. Halfhill - Senior Editor  {06/09/2003}

As the semiconductor slump lurches into its third year, more and more companies are seizing upon wireless communication as their savior. Just about the only other thing growing fast enough to justify a marketing department's hockey-stick graph is spam.

Relatively speaking, Intel isn't a recent convert to the wireless religion. The company most famous for its PC processors began investing heavily in communications in the mid-1990s by acquiring startups, absorbing competitors, and launching new product lines. (See MPR 9/13/99-01, "Intel Network Processor Targets Routers.") Intel's Centrino platform, delivered with the new Pentium M mobile processor in March, is an aggressive attempt to make wireless LANs pervasive in PCs. (See MPR 3/31/03-01, "Pentium M Hits the Street.") Now Intel is mapping an even more ambitious strategy to virtually eliminate the hardware cost of wireless integration by making digital radios inexpensive enough to build into almost any chip.

Two thrusts of the so-called Radio Free Intel initiative are a new microprocessor architecture and better radio integration with mainstream fabrication technology. The first goal is to create multiband communications processors that can automatically reconfigure themselves on the fly for different wireless standards—a necessity, says Intel, for a near-future world that will be saturated with multiple, rapidly evolving radio protocols. The other goal is to integrate a wireless baseband processor and analog front end on a single CMOS chip—without the extra costs and complications of external components, exotic semiconductors, or additional processing steps during fabrication. Ultimately, Intel wants to enable designers to integrate radios on their chips as freely as they integrate UARTs today.

Radio Free Intel is a long-term strategy, not a next-quarter cure for a becalmed semiconductor industry. It's a series of research and development projects managed by Intel's Corporate Technology Group, which reports to chief technology officer Pat Gelsinger. All told, the projects involve 50-60 people in Arizona, California, Oregon, England, Japan, and Russia. Eventually, they will hand the technology over to product groups for implementation. Although the engineers and executives leading these projects have laid some important groundwork, they admit they may not achieve some of their longest-term goals before they retire.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0609/172301.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Josh Fisher Wins Eckert-Mauchly Award
Tom R. Halfhill - Senior Editor  {06/09/2003}

Joseph “Josh” Fisher, a Hewlett-Packard senior fellow, will receive the prestigious Eckert-Mauchly Award this week at the International Symposium on Computer Architecture in San Diego, California. Fisher is winning the award for his pioneering work on VLIW microprocessor architectures.

In 1984, Fisher cofounded Multiflow, where he helped design one of the first VLIW computers. (See MPR 2/14/94-05, “VLIW: The Wave of the Future?”) Although Multiflow and both its closest competitors—Culler and Cydrome—ultimately went out of business, their seminal technology continues to influence the design of VLIW architectures. In 1990, Fisher joined HP to work on the PA-WW (Precision Architecture Wide-Word) project, which also used VLIW technology. In the mid-1990s, that project evolved into the Intel IA-64 architecture, jointly developed by Intel and HP. One of Fisher’s colleagues at HP Labs was the late Bob Rau, formerly of Cydrome, who won the Eckert-Mauchly Award last year. (See MPR 12/30/02-04, “VLIW Pioneer Bob Rau Dies.”)

Fisher earned his B.A. in mathematics at New York University and his M.S. and Ph.D. in computer science at New York University’s Courant Institute. In 1984 he won the National Science Foundation’s President’s Young Investigator Award, and in 1987 he won the Eli Whitney Connecticut Entrepreneur of the Year Award. The Association for Computing Machinery (ACM) and the IEEE Computer Society will present the Eckert-Mauchly Award and $5,000 prize to Fisher on June 10.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

Microsoft Details Secure PC Plans
Peter Glaskowsky - Editor-in-Chief  {06/02/2003}

Microsoft explained its new Next-Generation Secure Computing Base (NGSCB) initiative at the Windows Hardware Engineering Conference in May. NGSCB, due to ship with PCs based on Microsoft’s next major operating-system release (code-named Longhorn) in 2005, requires hardware changes to the CPU, core logic, and I/O devices. The NGSCB software stack is based on a secure “Nexus” that uses these updated hardware components— now being developed by AMD, Intel, and other companies—to enforce data security against any software-based threat. Hardware attacks are not part of the NGSCB threat model.

If Microsoft delivers on its NGSCB promises, the PC will become a safer and more reliable platform for both personal and professional uses. In discussions with Microprocessor Report at WinHEC, NGSCB architects admitted to weaknesses in the preliminary specification. Microsoft believes that trusted computing will create far more value in markets such as government, corporate, and financial computing systems. To satisfy these disparate markets, Microsoft must ensure a high degree of openness in the development of NGSCB software and hardware.

The advent of secure computing represents a substantial and long-overdue improvement in the computing industry. If this technology, even in significantly simpler implementations, had been adopted before the Internet phenomenon began, less time and money would have been lost to viruses, bugs, and piracy. Better late than never, however. We look forward to the arrival of NGSCB—and, we hope, a better name for it; the sooner, the better.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0602/172202.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Tensilica Patent Challenged
Tom R. Halfhill - Senior Editor  {06/02/2003}

MPR has learned that an unknown party is asking the U.S. Patent and Trademark Office to reexamine one of the patents on configurable development tools issued last year to Tensilica. The challenge doesn’t attempt to overturn the entire patent, but it does try to narrow the scope of about half the patent’s broadest claims.

The challenged patent is number 6,477,683, one of two issued to Tensilica on November 5, 2002, related to Tensilica’s customizable Xtensa microprocessor and automatic system for generating software-development tools. (See MPR 12/9/02-01, “Tensilica Patents Raise Eyebrows.”) The challenger of record is James Isbester, a patent attorney in Berkeley, California, who would not disclose the name of his client.

Tensilica—which learned about the challenge when contacted by MPR—declined to comment, other than to note that if the patent office turns down the request for reexamination, the decision will effectively strengthen the patent.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0602/172203.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.