Embedded Microprocessor Watch

Issue #165 -- 08/25/2003

Editor: Tom R. Halfhill

In this issue:

ARM Dons Armor
Tom R. Halfhill - Senior Editor  {08/25/2003}

“Trusted computing” is such a hot topic that a dictionary editor recently asked MPR if she should include the term in the next edition she’s compiling. Nothing validates a trend like the migration of technobabble to everyday language.

To make designing secure embedded systems easier, ARM is adding new security extensions to the ARMv6 architecture. The new TrustZone extensions are relatively simple, consisting primarily of one new instruction, a new configuration bit, and an additional permission level that supplements the existing user and privileged modes. TrustZone is simple because ARM’s objectives are limited. Instead of trying to make the entire system an impregnable fortress—a goal ARM considers unrealistic—TrustZone allows small amounts of security-critical code to run as a monitored process alongside the real-time operating system (RTOS) and application software. The secure context might be entrusted to handle encryption, decryption, authentication, certificate management, and other small but vital tasks.

ARM’s target applications are smartphones, handheld computers, and any embedded system likely to suffer from the malicious hackers who are expanding their attention beyond PCs. Wireless networking and field-upgradable software are opening new doors for intrusions, yet the typical embedded system has fewer system resources to spare for security measures than a PC has.

Although ARM says TrustZone’s architectural definition is final, the company continues to work with key customers, universities, and consultants to search for vulnerabilities and nail down the last details. ARM plans to implement the extensions in a new version of the ARM11 core, to be announced later this year. The first silicon implementations could appear by late 2004, followed by products in 2005. Going forward, TrustZone will be a standard feature of the ARMv6 architecture and future ARM cores.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0825/173401.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

3D Poised for Market Expansion
Peter Glaskowsky - Editor-in-Chief  {08/25/2003}

Now that 3D graphics have saturated the PC and workstation markets, graphics-chip companies are looking to leverage the technology they’ve developed for 3D rendering to create other products. Both high-volume and high-price opportunities exist, and both were widely visible at Siggraph 2003, held recently in San Diego.

Some of the most interesting new growth markets for 3D, in both large and small systems, were explored at Graphics Hardware 2003 (www.graphicshardware.org), an affiliated conference held the weekend before Siggraph. This writer chaired the conference’s Hot3D track for commercial hardware products, but even the research-oriented sessions at GH2003 included some very practical presentations.

The biggest volume opportunity for 3D—surpassing the PC market by a wide margin—is in handheld devices such as cellphones, PDAs, and games. Already, high-end cellphones, such as the DoCoMo D504i, have hardware 3D rendering and software support for the high-level Java 3D application programming interface (API). The D504i is based on the Z3D core from Mitsubishi, which was described at GH2003, along with a new core from Bitboys. We expect 3D to become a standard feature on all but the least expensive cellphones within the next three years, creating a sales opportunity for perhaps 500 million 3D processors per year.

At the other end of the price range, new graphics chips are expanding the market for systems costing $10,000 and up. “Powerwall” visualization systems are the hot ticket for designers of automobiles and other complex products. New commercial systems, such as HP’s sv7 and SGI’s Onyx4 UltimateVision, and new features in Nvidia’s Quadro FX3000 workstation graphics card, are cutting the price for powerwall systems and permitting much wider access to this technology.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0825/173402.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

It’s Time to Start Spending Again
Peter Glaskowsky - Editor-in-Chief  {08/25/2003}

The recession in the computer industry hit us all very hard. Intense price competition and reduced demand combined to have a terrible effect on revenues, forcing many of our companies to lay off workers and cut back on nonessential expenses. Unfortunately for In-Stat/MDR, some of our customers regarded this newsletter and our annual Forums as nonessential expenses.

During this same period, however, microprocessor vendors continued to design new chips, software companies continued to write new operating systems and applications, and OEMs continued to create new product categories requiring ever more sophisticated processors. Those of you who have been reading Microprocessor Report over the past three years have seen an unprecedented variety of new microprocessor architectures and implementations.

In the past 36 months, Microprocessor Report has covered more than 100 new microprocessors (not counting new speed grades) representing more than 80 distinct processor architectures. Most of these architectures also received their first detailed public disclosures in these pages. We’ve also published dozens of other articles explaining technologies and trends that will influence the development of future microprocessors, systems, and applications.

If you design microprocessors or microprocessor-based systems, this newsletter is not optional. Recession or no, this industry grows faster every year, and Microprocessor Report is the only comprehensive, objective source of information about all of the industry’s new developments. If you don’t have your own subscription, you should.

Microprocessor Forum and Embedded Processor Forum are also unique in this business. At MPF2003 this October, we’ll host presentations describing 20 new processors, cores, and architectures. If you’re not there, you’ll miss out on these presentations and the chance to discuss them with your peers. Instead of knowing, that week, which of these announcements matter to your company, you may need months to gather the information you require to proceed with your product-development programs. If you weren’t planning to attend, you should.

It may seem selfish of me to focus on our company, but this is the company I know best. Other conferences and publishers, however, have also suffered because of spending cutbacks. We’ve seen shows canceled or combined and other companies like ours shut down or sold off because they couldn’t survive the downturn. We’re pleased that we have the support of our parent company, Reed Business Information, and that we haven’t been required to shut down any of our products or services. Still, we have to show RBI that we can recover along with the rest of the semiconductor industry.

So it’s time for all of us to loosen the purse strings on our research and training budgets, authorize more travel to important industry events, and catch up on all the good work that’s been taking place in this business since the recession began. Believe that we will see a return to strong growth in the semiconductor industry, and we will. Don’t expect 40% growth rates—don’t even expect 20% next year—but we can and will resume growing faster than the rest of the world and national economies.

Semiconductors, and especially microprocessors, have a long way to go before they realize their full potential for improving our daily lives and industrial productivity. As we find new ways to benefit from intelligent devices and improved communications networks, we’ll need ever more specialized chips. It’s our job here at In-Stat/MDR to explain this progress, and we look forward to doing this work for you.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

Xelerated’s Xtraordinary NPU
Peter Glaskowsky - Editor-in-Chief  {08/18/2003}

The world’s first 40Gb/s network processor, the Xelerator X10q from Xelerated, uses a programmable pipeline of unprecedented depth to perform forwarding and filtering functions on up to 100 million packets per second. The chip contains 200 identical processor cores pipelined together with interfaces to memory and function units. For the first time, Xelerated has released details of the X10q that show how the company was able to make such a complex design work, and how Xelerated’s customers can develop software for the chip.

During each clock period, each of the X10q’s processors executes one VLIW instruction that encodes up to four operations and transfers the results of these operations, plus the rest of its register and packet data, to the next processor or engine access point (EAP). The EAPs have multiple pipeline stages to accommodate the latency of the various function units and memories. There are about 1,040 stages through the X10q’s processor core.

When processing packets at the maximum rate, the 200 processors together achieve a maximum processing rate of 80 billion operations per second. This rate is about three times the processing power of Intel’s 10Gb/s IXP2800 NPU running at 1.4GHz, though the IXP2800 has a more flexible (and less deterministic) programming model. The aggregate data flow in the pipeline is 1,008 bits ´ 1,040 stages per clock, or 26.2 petabytes per second at 200MHz.

With most of Xelerated’s competitors focusing on 2.4Gb/s and 10Gb/s applications, the X10q may lack any direct competition until late 2004, by which time Xelerated could be on its second generation of products. Unfortunately, there will be few customers at these higher speeds until 2005, or possibly later, depending on the way the communications business recovers from its current slump. In the meantime, the X10q can be used to connect multiple 10Gb/s channels to a single network switch. Xelerated has excellent technology, but it will also need excellent patience and stamina to survive.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0818/173301.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

MediaQ’s Silicon Katana
Max Baron - Principal Analyst  {08/18/2003}

On May 19, MediaQ introduced Katana, officially known as the MQ-9000 family, designed to offer OEMs a complete system solution on one chip. Simple as it may seem at first glance, adding a processor core on chip carries with it system responsibilities that MediaQ has hitherto left to the system designers using its graphics and peripherals chips. System peripherals like SPI, keypad interface, and UARTs had to become part of the MQ-9000. The ARM processor’s performance was increased by adding a Java accelerator. Most important, however, the company’s design team had to minimize the effects of on-chip bus contention among accelerators and CPU. MediaQ’s chips must be able to compete successfully against existing offerings, most of which are second- and third-generation designs profiting from system designers’ and end-users’ feedback.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0818/173302.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Breaking Embedded System Barriers
Markus Levy - Senior Editor  {08/11/2003}

Continuing advances in manufacturing processes have made it possible for processor vendors to build increasingly faster processors. In this context, faster refers to megahertz and does not necessarily imply faster performance. In fact, many barriers stand in the way of achieving faster performance, despite the ever-increasing megahertz ratings of embedded processors. At EPF 2003, a panel comprising processor architects, compiler developers, operating-system vendors, and a system-level expert discussed the key challenges and trends facing embedded-system designers.

To start the discussion, I asked each panelist to provide a short synopsis of what he considered the most important revolutionary and/or evolutionary factors in embedded-processor, compiler, or operating-system technology. The panelists focused on the primary topics of symmetric multiprocessing, hardware-based multithreading, compiler optimization techniques, memory subsystem enhancements, and interconnect technology (such as RapidIO).

Because of today’s economic conditions, the number of large microprocessor-architecture teams has arguably diminished. However, the number of semicustom and derivative designs has wildly mushroomed, employing far more CPU architects and designers today than ever before. I believe this trend spells out innovation, and although the direction embedded processors will take is somewhat unpredictable, it is certain the design community will provide solutions for the technical challenges that arise. This article highlights the challenges that system designers will face and the solutions that will help them to be successful.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0811/173201.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

ARM Wrestles With MIPS
Markus Levy - Senior Editor  {08/04/2003}

When ARM and MIPS designed their latest microarchitectures, both companies had a common goal of achieving clock frequencies higher than in their prior-generation microarchitectures. For ARM, this meant its ARM11 would be able to outclock the six-stage ARM10 pipeline. For MIPS, this meant its 24K would have to outrun the five-stage pipeline of its 4Kx and the 5K’s six-stage pipeline. The simple solution was to add a few pipeline stages, and, consequently, both the ARM11 and the 24K have eight-stage pipelines.

Not surprisingly, both synthesizable microarchitectures will hit a frequency range of 400–550MHz (worst case) when fabricated in a 0.13-micron process. Both microarchitectures, with single pipelines, will typically execute less than one instruction per clock. Therefore, at a given clock frequency, the ARM11 and MIPS 24K should have roughly the same levels of performance. However, each microarchitecture incorporates a variety of design tradeoffs that yield differences in instructions per clock.

In this article, we compare and contrast the different microarchitectural features of the ARM11 and MIPS24K. As expected, there are similarities, but there are also distinct differences. For example, going with a synthesizable design, both ARM and MIPS faced the same bottlenecks associated with cache lookup times. Therefore, the ARM11 and the MIPS24K are similar in that their designs center on memory accesses. On the other hand, the MIPS branch predictor uses a 512-entry two-bit branch history table (BHT), but the ARM11’s BHT contains only 128 entries. However, in the ARM11, if the dynamic branch predictor cannot find a record of the branch instructions, a static branch prediction mechanism takes over. The article contains other examples that will help the reader understand the capabilities of these microarchitectures.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0804/173101.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Rambus Yellowstone Becomes XDR
Peter Glaskowsky - Editor-in-Chief  {08/04/2003}

About a year after previewing its next-generation memory-interface technology, code-named Yellowstone (see MPR 7/15/02-01, “Rambus Rolls Out Yellowstone”), Rambus has unveiled final specifications, fab partners, and a formal name: XDR DRAM, expressing the specification’s “extreme” data rate.

XDR memory (www.rambus.com/xdr) will be offered initially by Toshiba and Elpida, both of which expect to begin shipping samples in 2004, with high volumes planned for 2005. Rambus and its partners will be pursuing many kinds of customers for XDR. Some, such as graphics and networking companies, will be easy to persuade. The PC main-memory market will be harder to crack.

Even if Rambus can’t get onto PC motherboards, XDR should sell well into all performance-hungry systems that require only moderate amounts of memory—say, from four to eight DRAM chips. Game consoles and graphics cards may represent the majority of such systems, but Rambus will be kept busy pursuing dozens of smaller opportunities that, together, add up to significant unit volumes.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2003/0804/173102.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.