Embedded Microprocessor Watch

Issue #168 -- 11/24/2003

Editor: Tom R. Halfhill  

In this issue:

What’s Microsoft’s Game?
Peter Glaskowsky - Editor-in-Chief  {11/24/2003}

Microsoft is a software company, but it does more hardware design than many hardware companies do. Microsoft recently made several key announcements related to the second generation of its Xbox videogame console, and these announcements make it clear the company is taking an entirely new approach to creating the new system. Today’s Xbox is much like a standard x86 PC; its components were state of the art when Xbox shipped, but today they’re simple commodities.

The next Xbox—reportedly to be called Xbox Next—will combine graphics technology from ATI with core logic from SiS to replace the integrated-graphics chip set designed by Nvidia for the original Xbox. Neither of the new partners will provide actual chips; Microsoft will use ATI and SiS circuit designs in new custom ASICs.

The processor picture for the new machine is less clear. Microsoft has licensed PowerPC processor technology from IBM for the new Xbox, but no further information has been released. The particular core could be IBM’s PowerPC 970, the PowerPC 440 used in high-end embedded systems, or some unannounced design. It’s even possible Microsoft will use more than one PowerPC core, but the company hasn’t said.

Microsoft also declined to specify whether the selected core will be the only general-purpose processor in the system. Without an x86 processor, maintaining software compatibility with the original Xbox will be more difficult. Microsoft gained in-house emulation technology through its acquisition of Connectix earlier this year, but emulating a 733MHz Pentium III with sufficient reliability to host performance-intensive videogames would require a far more powerful RISC chip—probably at least a 3GHz device. Multiple slower cores would not work.

To solve this problem, Microsoft could add another processor core, an x86 design licensed from AMD, Intel, or VIA. Xbox currently has a programmable graphics core and an audio DSP coprocessor; Microsoft could presumably adopt a more-complex heterogeneous multiprocessing configuration for the next-generation system. There’s no hint of such a strategy from Microsoft, however appealing it may be. Such a multicore design could enable the concurrency needed to use Xbox Next as a digital video recorder or home multimedia gateway.

Integrating processors, core logic, graphics, and peripherals to create an all-new videogame platform is no easy task, no matter how mature the individual cores Microsoft has licensed. To make Xbox Next competitive against Sony’s forthcoming PlayStation 3, Microsoft will need three or four complex chips, totaling several hundred million transistors. A project of this magnitude could keep a large design team busy for years. Microsoft’s deal with IBM could be tied to IBM’s expertise in custom SoC designs, but we don’t know how much of the design work for the new Xbox—if any—could be handled by IBM.
The company’s investment in new Xbox hardware could approach half a billion dollars, and that figure doesn’t include software development or marketing expenses. I don’t know if Nintendo can afford to match this kind of spending. Sega dropped out of the console competition when Microsoft joined; will Nintendo be the next to give up on hardware to focus on game development?

In creating Xbox Next, Microsoft will gain considerable skills and experience in system-on-chip design. Although it’s unlikely the company would offer chips to the merchant market, Microsoft would effectively become a fabless semiconductor company. These skills could allow Microsoft to pursue other markets, where it has previously relied on external design firms. Microsoft may not need to partner with other companies to pursue markets such as set-top boxes and cellphones, where systems are generally sold through service providers rather than at retail. If Microsoft doesn’t need retail-focused OEMs to sell its designs—as it does in the PC and PDA markets—it may choose to cut out the middlemen and boost its profits. Microsoft could be a fearsome competitor for many companies that today are its partners.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

Motorola Revs Engine Controller
Peter Glaskowsky - Editor-in-Chief  {11/24/2003}

The growing demand for high-performance, high-efficiency car and truck engines is driving the creation of more-complex microcontrollers to manage engine operation. Motorola is a market leader in this area, with its MPC500 power-train controllers, and recently launched the first member of its new MPC5500 family, the MPC5554.

The chip includes a virtual “parts department” of other peripheral functions, including SRAM, 2M of flash memory, a 64-channel DMA controller, dual enhanced time-processor units, and dual analog-to-digital converters.

The e500 core is the first of Motorola’s Book E–compliant core designs. A preliminary product brief for the MPC5554 gives core clock rates up to 132MHz, but general availability of the chip will not begin until 4Q04, so this may not be the final word on clock rates. Pricing information is also about a year away. More information is available online at e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC5554.

Microprocessor Report readers can access the full story here (<1 page, news item): www.mdronline.com/mpr/h/2003/1124/174703.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Floating Point Buoys ClearSpeed
Tom R. Halfhill - Senior Editor  {11/17/2003}

Once upon a time, there was a thriving market for floating-point math coprocessors—until Intel’s 486 and other general-purpose processors integrated the FPU on chip, eventually sinking coprocessor companies like Weitek. Since then, the major CPU vendors have set the pace for floating-point performance. If you need more performance than integrated FPUs can deliver, the only alternatives are multiprocessor servers or supercomputers, custom logic in ASICs or FPGAs, or a few relatively unknown and exotic CPU architectures.

ClearSpeed fits the last category. In the Extreme Processors session at Microprocessor Forum 2003, the U.K.-based startup revealed a new massively parallel CPU architecture intended to revive the market for floating-point coprocessors. ClearSpeed’s strategy is to offer much higher floating-point performance at much lower power levels than general-purpose CPUs, enabling designers to build faster embedded systems and accelerator cards for PCs, workstations, and servers. Instead of bottom-trawling for the mass market, though, ClearSpeed is fishing for customers willing to spend $975 per chip for 25.6 billion floating-point operations per second (GFLOPS).

In price and floating-point performance, ClearSpeed’s new CS301 chip appears to compete against Intel’s Itanium-2, IBM’s Power4, Sun’s UltraSparc III, and high-end x86 processors from AMD and Intel. The CS301 is a coprocessor, however, not a standalone CPU, and it’s far more suitable for embedded systems than are any of the aforementioned chips, thanks to miserly power consumption in the 1.8–2.5W range. Nobody can beat 10 GFLOPS per watt.

However, the CS301’s potential for sustaining its superlative peak performance is suspect. The bottleneck will likely be I/O bandwidth to main memory, at least in certain kinds of applications. With a 64-bit bidirectional bus that runs at 200MHz, the CS301 provides only 1.6GB/s of off-chip memory bandwidth in either direction, or 3.2GB/s of aggregate memory bandwidth. (Two bridge ports provide another 1.6GB/s of aggregate I/O bandwidth, but only with other CS301 chips in multiprocessor designs.) For most floating-point applications, 3.2GB/s seems like insufficient plumbing for a massively parallel processor that has 128 FPUs.

The ideal system would be designed around the CS301, much as Japan’s Earth Simulator supercomputer is designed around NEC’s custom ES microprocessors. The cool-running CS301 lends itself to a massively parallel system architecture that packs dozens or hundreds of chips into a small space. Server blades that plug into a high-bandwidth backplane are another possibility. An extreme processor deserves an extreme system architecture.

Microprocessor Report readers can access the full story here (6+ pages, 4 figures): www.mdronline.com/mpr/h/2003/1117/174601.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Jupiter’s Twin Cores
Max Baron - Principal Analyst  {11/17/2003}

Motorola SPS is launching a new architecture, a new approach to SoC design, and a business strategy to match. Motorola SPS is calling its new brainchild the Mobile Extreme Convergence (MXC) Architecture. Motorola’s new architecture will deliver sufficient performance and integration to reduce the number of chips required to build air communications for handheld devices, simplifying the software required for their operation. Designed to Motorola’s MXC architecture specifications, a new chip named Jupiter employs an ARM1136JF-S and a StarCore SC140e DSP, supported by a high-performance on-chip memory hierarchy and crossbar interconnects.

Although primarily aimed at air communications such as cellular, Wi-Fi, and Bluetooth, Motorola’s approach may find additional markets in the consumer, automotive, and industrial segments.

Microprocessor Report readers can access the full story here (6 pages, 6 figures): www.mdronline.com/mpr/h/2003/1117/174602.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Will Microprocessors Become Simpler?
Don Alpert  {11/17/2003}

The history of processor architecture has experienced several cycles in which following the path of conventional wisdom has led to increasingly complex designs until better, simpler solutions emerged. During the years since the 1980s, the simple RISC architectures of that decade have evolved into complex implementations having high-frequency, superscalar, out-of-order speculative execution engines enabled by elaborate branch-prediction schemes and multilevel caches. We believe that the trend toward simpler architectures has again arrived—at least for workloads having high thread-level parallelism (TLP) and poor locality.

Commercial workloads, such as on-line transaction processing (OLTP), have such large working sets that enhanced pipeline techniques, such as superscalar execution, deliver marginal performance improvement. Multithreading is a technique that allows a single processor to overlap memory accesses from independent processes. Several design examples show that simple processors employing multithreading can demonstrate better cost-performance for commercial workloads than do more-complex processors optimized for workstation workloads.

Microprocessor Report readers can access the full story here (3+ pages, 1 figure): www.mdronline.com/mpr/h/2003/1117/174603.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Multithread Technologies Disclosed at MPF
Markus Levy  {11/10/2003}

Although multithreading has long appeared to be a good solution for the mismatch between processor speed and memory bandwidth, the embedded industry has been slow to adopt this technology. This reluctance can be attributed to issues such as the lack of software support, the extra silicon expense, and the use of stopgaps such as DDR memory and larger caches. But the tide may be turning, as witnessed at Microprocessor Forum 2003, as several companies, including Imagination Technologies and MIPS, used this conference as the springboard to launch multithreading products and technologies.

On the surface, the Imagination Technologies META processor is a standard 32-bit architecture that supports both RISC and DSP instructions. The processor has a modular design, typically containing two 32-bit data units, two 32-bit address units, and a control unit. META’s DSP extensions are many of the features found in a full-fledged DSP. The processor implements a system of instruction “template” registers that generates a robust DSP instruction set without requiring an excessively long instruction word.

The most significant feature of the processor is that it maintains a number of separate hardware execution threads. Multithreading allows the META processor to switch contexts in response to rapid real-time events without software overhead. The META processor’s thread-switching ability is based on complex heuristics. The core of a multithreaded system is the hardware scheduler, which determines which threads will be activated. On every cycle, the META scheduler examines the next candidate instruction from each thread and chooses which one to execute. To make this choice, the scheduler considers the availability of more than 50 internal processing resources and a thread prioritization system.

Although MIPS has not yet given out many specific details on actual implementation, the bottom line is a definition of multithreading using a hierarchical approach. At the simplest level, MIPS has developed multithreading semantics that will operate inside an instruction-set architecture that will provide a possibility of expressing to hardware the parallelism of a program in ways that couldn’t be done otherwise. This will allow fine-grain multithreading without a great deal of overhead and anticipate the migration of threads for multithreaded and multiprocessor designs.

Microprocessor Report readers can access the full story here (4 pages, 2 figures): www.mdronline.com/mpr/h/2003/1110/174501.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

MDR Reorganized, Ready for 2004
Peter Glaskowsky - Editor-in-Chief  {11/10/2003}

We’ve made several changes on the MDR side of In-Stat/MDR. Most important, Markus Levy is no longer on our staff. Markus’s primary area of coverage, high-performance embedded processors, will be shared among our other analysts. We thank Markus for his excellent work for us over the years, and we’re sure we’ll be working with him in the future as he continues in his role as president of EEMBC. Markus has joined the Microprocessor Report editorial board, and we hope he will contribute occasional articles to the newsletter.

Kevin Krewell has returned to full-time analyst duties at his request, giving him more time for his work on Microprocessor Report and the Intel Microprocessors service. Assuming the role of general manager for MDR is Frank Dickson, previously senior director of sales and marketing and principal analyst with In-Stat/MDR.

We believe these changes will strengthen our company as we enter 2004. If you have any questions about them, please write to me at png@reedbusiness.com.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

Philips Powers Up for Video
Tom R. Halfhill - Senior Editor  {11/03/2003}

With an eye on the growing market for consumer electronics, Philips Semiconductors announced a new TriMedia 32-bit processor core at Microprocessor Forum 2003. The swifter core will debut next year in Philips media processors destined for personal video recorders, wireless networks, high-definition TVs, and other audio/video products.

Unlike some previous TriMedia CPU cores, the new TM5250 won’t be offered as licensable intellectual property (IP). Philips shut down its TriMedia Technologies IP-licensing business last year. (See MPR 5/19/03-03, “TriMedia Comes Home.”) Instead, the TM5250 will spawn a new generation of standard-part Nexperia media processors designed and manufactured by Philips.

The TM5250 is source-code compatible with processors based on TriMedia’s DSPCPU32 architecture, which dates to 1994. (Actually, the architecture has an even longer history that stretches back to the Philips LIFE project in 1987; see MPR 12/5/94-03, “Philips Hopes to Displace DSPs with VLIW” and MPR 8/8/90, “Philips Gives LIFE to VLIW”.) Source-code compatibility provides a migration path for current customers of TriMedia 32-bit processors in the TM1000, TM1100, and Nexperia PNX1300 families. The TM5250 is not compatible with the 64-bit DSPCPU64 architecture announced in 1998 (see MPR 10/26/98-07, “Philips Advances TriMedia Architecture”), but it doesn’t matter, because Philips has never introduced an implementation of that architecture. Instead, Philips has decided to improve the performance of the 32-bit architecture while maintaining compatibility with existing TriMedia processors.

New features in the TM5250 include superpipelining, nine new instructions for video processing, improved L1 caches, an integrated L2 data cache, better prefetching, and a larger array of function units that can keep as many as 29 pending instructions in flight.

The TM5250 is a fully synthesizable CPU core based on a standard-cell logic library and standard, single-ported SRAMs for the caches. Philips expects the CPU to run at 500–700MHz and occupy 19.8mm2 of silicon when fabricated in a standard TSMC 0.13-micron six-layer-metal process. According to estimates obtained from a Philips gate-level simulation tool and Synopsys PowerTheater, the TM5250 will consume less than 2mW per megahertz, or about 1W at a conservative target clock speed of 500MHz. A chip based on the new CPU core will be announced early next year.

Microprocessor Report readers can access the full story here (5+ pages, 4 figures): www.mdronline.com/mpr/h/2003/1103/174401.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.