Embedded Microprocessor Watch

Issue #169 -- 12/29/2003

Editor: Tom R. Halfhill  

In this issue:

Sonics Gains Acceptance
Tom R. Halfhill - Senior Editor  {12/22/2003}

Since its founding in 1997, Sonics has been gradually establishing its on-chip interconnect technology among important customers like Broadcom, Flextronics, Fujitsu, Hitachi, Hughes, Intel, NASA, NEC, Nokia, Samsung, Texas Instruments, and Toshiba. Last fall, TI licensed additional Sonics technology for its OMAP wireless-communication processors, and an industry-standards body adopted the core-interface protocol backed by Sonics.

Numerous companies now license ready-to-use intellectual property (IP) in the forms of hard macros or synthesizable processors and peripheral cores. Integrating IP from different vendors isn’t a straightforward task, however, because the on-chip interfaces are so variable. Sonics stands at the intersections between those IP components. Its own licensable IP consists of switched-fabric interconnects, sockets, and design tools for integrating other vendors’ core IP on SoCs.

Sonics’ latest product is SiliconBackplane III, a new version of its interconnect fabric. SiliconBackplane III isn’t just another bus that competes with ARM’s AMBA, IBM’s CoreConnect, and similar buses for core IP. Instead, it’s a micronetwork with some native intelligence that can work with any core-IP interface. Companion products include Synapse 3220 Peripheral Interconnect IP (introduced in 2002), MemMax Memory Scheduler IP (introduced at Microprocessor Forum in 2001), and Sonics Studio, an SoC design-integration tool.

The company received a major boost in October when the core-interface protocol it supports was adopted by an important industry-standards body, the Virtual Socket Interface Alliance (VSIA). VSIA endorsed the Open Core Protocol (OCP)—which is controlled by the OCP International Partnership, an independent trade organization—as a standard socket for connecting on-chip components. Sonics is a longtime supporter of OCP and uses the socket to connect IP cores to its SiliconBackplane III, Synapse 3220, and MemMax products.

Microprocessor Report readers can access the full story here (3 pages; 1 figure): www.mdronline.com/mpr/h/2003/1222/175101.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.www.mdronline.com.

ARC Alters Trajectory
Tom R. Halfhill - Senior Editor  {12/15/2003}

ARC International was the first to license a customizable microprocessor core, but financial success has been elusive, and new competitors keep emerging. In a bid to regain the initiative, ARC has extensively revamped its product line and is pursuing a wider range of customers by offering preconfigured cores.

The most significant announcement is a successor to the ARCtangent-A5 microprocessor core, the company’s two-year-old flagship product. The new ARC 600 core adds static branch prediction, more power-saving features, and a deeper pipeline that boosts the clock frequency by as much as 45%—to 290MHz in a 0.13-micron fabrication process. Like the ARCtangent-A5, the ARC 600 is a synthesizable 32-bit RISC processor that customers can configure and extend for specific applications and then implement in an SoC, ASIC, or FPGA.

New or improved hardware-development tools make it easier for customers to optimize the ARC 600 for their applications. ARC’s graphical processor-configuration tool, ARChitect, has received a major facelift and is now called ARChitect 2. A new “wizard” tool streamlines the task of merging custom extensions with the synthesizable model of the ARC 600. A new hardware/software cosimulation tool allows developers to run the ARC 600 instruction-set simulator alongside the software debugger and register-transfer-level (RTL) simulations of external logic. Software programmers get some goodies, too: ARC has revised the entire MetaWare software-development tool chain for the ARC 600, including the addition of compiler optimizations that exploit the deeper pipeline and branch prediction.

Providing a user-customizable processor is still central to ARC’s business strategy, but the company has decided to also offer preconfigured CPU cores for vertical applications. ARC sees more customers asking for a complete “platform” of licensable intellectual property (IP): a soft microprocessor core already customized for a popular application domain, peripheral soft-IP, supporting middleware, development tools, and perhaps some system software. To capture that lucrative business, ARC will offer new platforms of preintegrated IP as an additional licensing option. The first example is an ARC 600 processor with new hardware extensions and software codecs designed for portable digital-audio products, mainly MP3 players.

All these announcements strengthen ARC’s competitive position against its chief rivals—ARM, MIPS Technologies, and Tensilica—as well as against some newcomers to soft-IP licensing, such as Octera and Silicon Hive. Although ARC can rightfully boast of an increasingly comprehensive product line, none of the new products will give ARC a decisive advantage. Therefore, ARC’s fortunes remain tied to its struggle toward profitability and the general health of the industry.

Microprocessor Report readers can access the full story here (6 pages; 3 figures): www.mdronline.com/mpr/h/2003/1215/175001.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Awards Nominees Announced
Peter Glaskowsky - Editor-in-Chief  {12/15/2003}

We are pleased to announce the following nominations for the 2003 Microprocessor Report Analysts’ Choice Awards. Our categories this year represent the most-interesting and -dynamic product areas in the microprocessor industry, and the nominees in each category represent the best of the best. To be selected as a nominee, products must have been available in sample or production quantities during 2003; cores must be available for licensing.

Some categories—notably those for low-power embedded, extreme, and application processors—reflect important changes in our industry over the course of the year. The levels of integration and performance in these products have increased dramatically, enabling not just new systems but whole new classes of systems, especially in the consumer electronics and networking industries.

We’ll be announcing the winners of these awards during a dinner presentation on February 5, 2004, at the Il Fornaio restaurant at the Hyatt Sainte Claire in San Jose, California. Advance registration is required for this event. To register, visit www.MDRonline.com/events/dinner or call 480-483-4441.

These nominations are based on the best public information currently available to our analysts. We are tracking a few products that may begin customer sampling by the end of 2003; we’ll make sure our final selections, and our year-in-review articles for Microprocessor Report, incorporate any new information that becomes available to us.

The categories and nominees:

Desktop Processors:
AMD Athlon 64 FX-51
IBM PowerPC 970
Intel Pentium 4

Mobile PC Processors:
AMD Mobile Athlon 64
Intel Pentium M (Dothan)
Transmeta Efficeon TM8000

Server Processors:
AMD Opteron 848
IBM Power 5
Intel Itanium 2
Intel Xeon MP

Low-Power Embedded Processors:
Analog Devices ADSP-BF533
Infineon TriCore 2
Intel PXA800F
Texas Instruments TBB4105

Application Processors:
Intel XScale PXA260
NeoMagic MiMagic 6
Nvidia MQ-9000
STMicroelectronics Nomadik STn8800
Texas Instruments OMAP 1611

High-Performance Embedded Processors:
IBM PowerPC 750GX
Intrinsity FastMIPS
Motorola PowerPC MPC7457
Motorola MPC8560 PowerQUICC III
PMC-Sierra RM9000x2
Raza Microelectronics XL7105

Media Processors:
Equator BSP-15
Intel MXP5800
Motorola MRC6011
Philips TriMedia TM5250
Silicon Hive Avispa+

Extreme Processors:
ClearSpeed CS301
Cradle ECE3400/MPE3400
Intrinsity FastMATH
Toshiba ET1
Xelerated X10

Soft-IP Processor Cores:
ARC International ARC 600
ARM ARM1136JF-S
MIPS M4K Pro
Silicon Hive Avispa+
StarCore SC1400

Best Technology:
Microsoft Next-Generation Secure Computing Base
Reconfigurable processing
Tensilica automatic processor-extension generator
Transmeta LongRun 2

To find out more about Microprocessor Report, please visit: www.mdronline.com.

Roll Your Own Array Processor
Peter Glaskowsky - Editor-in-Chief  {12/15/2003}

Sometimes an ASIC is too hard, an FPGA is too soft, and one needs more processing power than a conventional microprocessor can offer. MathStar, in its presentation at Microprocessor Forum 2003, described a new kind of array processor built from a set of standard elements. According to the company, a single chip just 100mm2 in size, built in TSMC’s 130nm LVOD process, can deliver up to 400 GOPS of theoretical peak throughput on about 20W of power.

Using its own Field Programmable Object Array (FPOA) architecture, MathStar creates arrays from 10 types of standard objects, including computational elements, register files, memory arrays, and external interfaces. The ALU and multiply-accumulate objects operate on 16-bit input data at internal speeds as high as 1GHz. These objects are interconnected using uniform packetized data buses.

MathStar says products based on its FPOA chips—the first of which has taped out and should begin sampling in January 2004—are easier to design than ASICs or FPGAs and are much faster than ordinary microprocessors. Furthermore, they eliminate the mask costs associated with ASIC designs. The merits of the FPOA approach depend strongly on the specific application, of course. Algorithms well suited to highly regular structures will be easier to implement than those consisting of more-random logic. MathStar has not announced pricing or production availability. More information on the company’s products is available at www.mathstar.com.

Microprocessor Report readers can access the full story here (1 page): www.mdronline.com/mpr/h/2003/1215/175003.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

IDT Expands ICP Line
Peter Glaskowsky - Editor-in-Chief  {12/08/2003}

IDT’s Interprise family of integrated communications processors has a new member, the RC32434. The RC32434 has a 32-bit MIPS processor capable of 400MHz operation, one Ethernet interface, a 16-bit DDR SDRAM controller, a PCI bridge, and assorted peripherals. Unique to this member of the Interprise family is a 64-byte nonvolatile RAM (NVRAM) array with an “authentication unit” that protects the content of the array. Unless a predetermined key value is presented to the authentication unit, the NVRAM data can’t be read or modified.

Such a combination is not revolutionary in this market. Other highly integrated network processors, such as Intel’s IXP425, offer a similar—or higher—level of integration. What’s more important to IDT’s customers is that this new chip is part of an unusually broad family, all with compatible cores and similar programming models. IDT now has nine different Interprise offerings, priced from $10 to $35.

TSMC manufactures the RC32434 for IDT in a 130nm process. The chip comes in a 256-contact ball-grid array package. Four speed grades are offered, from 266MHz to 400MHz, priced from $15.50 to $23.

There are many competing vendors, architectures, and products to choose from when selecting integrated processors for networking systems. No single vendor can hope to engage the whole market, because many potential customers are locked into one architecture. IDT is doing everything a vendor can do to attract customers to its architecture, using a wide range of chips, features, and prices.

Microprocessor Report readers can access the full story here (2 pages, 2 figures): www.mdronline.com/mpr/h/2003/1208/174901.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Silicon Hive Breaks Out
Tom R. Halfhill - Senior Editor  {12/01/2003}

Parallel lines never meet, but great minds think alike. Maybe that explains the convergence of parallel processors at this year’s Microprocessor Forum and Embedded Processor Forum. All over the world, maverick CPU architects are trying to exploit their soaring transistor budgets for something besides humongous on-chip caches.

The latest example—announced during the Extreme Processors session at Microprocessor Forum 2003—is a configurable parallel-processing architecture from Silicon Hive, a Netherlands-based startup funded by Philips Electronics. Silicon Hive has created what it calls an ultralong instruction-word (ULIW) architecture—an apt description. As with a very long instruction-word (VLIW) architecture, a special compiler bundles multiple operations together for simultaneous execution on a target processor. But with instruction words that stretch up to 768 bits long, each containing scores of operations, Silicon Hive’s ULIW architecture surpasses every known VLIW machine. It’s also highly configurable, allowing designers to alter almost every feature for optimum performance in vertical applications.

To support this unusual architecture, Silicon Hive has created a whole ecosystem: a tool chain for rapidly designing custom ULIW cores, a library of function units for designers to choose from, and adaptive software-development tools. Putting theory into practice, the company has developed two ULIW-based cores for licensing as synthesizable intellectual property (IP). Known as the Avispa (“wasp” in Spanish) and Avispa+, the preconfigured cores are designed for signal processing in orthogonal frequency-division multiplexing (OFDM) radio applications.

As a measure of what’s possible with this architecture, Avispa+ can execute nine billion operations per second (GOPS) at a clock frequency of only 150MHz. When Avispa+ is fabricated in a 0.13-micron bulk CMOS process, core voltage is 1.0–1.05V and power consumption only about 150mW under worst-case military conditions (125°C). The processor core will occupy a mere 4mm2 of silicon. Although 150MHz is on the lower end of the clock-speed spectrum, the other statistics are impressive for a fully synthesized, standard-cell design that can issue 60 operations per clock cycle.

What’s more, Silicon Hive says its proprietary tool chain can generate similar processor cores to customer specifications in a matter of days. The company’s first customer (not yet publicly announced) expects to tape out an SoC with a customized ULIW core this quarter. That chip will be a media processor that replaces several ASICs in a low-end MPEG4 application. It may also be used for image stabilization in a mobile-phone video camera.

Microprocessor Report readers can access the full story here (6+ pages, 5 figures): www.mdronline.com/mpr/h/2003/1201/174802.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.