Embedded Microprocessor Watch

Issue #170 -- 01/26/2004

Editor: Tom R. Halfhill  

In this issue:

New EDGE Chip Set From TI
Max Baron - Principal Analyst  {01/26/2004}

TI’s new TCS3500 smartphone chip set, the third generation in this product family,  adds support for EDGE (Enhanced Data Rates for GSM Evolution) communications. TI says the TCS3500 with EDGE will provide up to three times the data throughput of earlier GSM/GPRS chip sets in the series, making it the preferred choice for bandwidth-hungry applications such as multimedia, digital cameras, video, and games. Wireless LAN and Bluetooth are optional add-ons.

TI is providing TCS3500 customers with a tested reference design to which it has already ported the most-popular operating systems, such as Java, Linux, Nucleus, Palm, Symbian OS, and Microsoft’s Windows Mobile.

The most significant new chip in the set is the OMAP850, which combines a high-performance application processor and a GSM/EDGE DSP modem on the same chip. The OMAP850 maintains the secure environment of the current generation of OMAP processors, including secure boot, a secure execution environment, and hardware encryption accelerators.
Chip-set pricing has not been announced. TI expects to ship samples of the TCS3500 in 1Q04; volume production is expected in 4Q04. For more information, please visit www.ti.com.

Microprocessor Report readers can access the full story here (3 pages; 1 figure): www.mdronline.com/mpr/h/2004/0126/180401.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

ES Strains Seams, Credulity
Peter Glaskowsky - Editor-in-Chief  {01/26/2004}

After two years of echoing emptiness at Comdex Fall, the bustling crowds at January’s Consumer Electronics Show, straining the seams of the Las Vegas Convention Center, were almost too much to handle. It was a great show for microprocessor developers; all the best products at CES are microprocessor controlled, and many strain the limits of processor technology.

Microsoft chairman Bill Gates announced a substantial expansion of the company’s Media Center PC concept, with three new products designed to allow the sharing of digital content throughout a home. A new low-cost Media Center Extender set-top box will use Microsoft’s Remote Desktop Protocol (RDP) as a remote display device for any Media Center PC on the local network, providing the same Media Center user interface as the PC but without the need for local storage. The Media Center Extender can be much smaller and cheaper than a PC, so customers can afford to buy one for every TV in the house—at least, that’s Microsoft’s hope.

For those who already have a Microsoft Xbox, or who might be willing to buy one for this purpose, Microsoft will offer a Media Center Extender kit, consisting of a remote control and a DVD with the RDP software. Like the set-top box, an Xbox running this software will provide the Media Center PC user interface, but at a much lower cost per TV.

Finally, those who want their video to go will be able to get a Portable Media Center. Gates showed a prototype model from Creative. Though bulky, presumably because it needs a large battery to achieve reasonable operating times, the Zen Portable Media Center may do better on the market than current products that lack Microsoft’s support. Creative plans to ship the device in 2H04 at a price of $499 with a 20G hard disk.

Some products at CES strained our credulity, especially those in the home and car audio markets. Fortunately, there were no eardrum-straining indoor demonstrations of just how powerful today’s subwoofers are, but many companies were offering models that could easily double as lithotripsy machines for breaking up kidney stones without surgery.

What bothered me more than any of these products were the ridiculous claims of vendors of high-end interconnect devices. (We define “interconnect” as an audio or video cable that costs far more than it’s worth.) At least one company at CES was showing audio cables with a battery holder and an extra center conductor to apply a DC electric field across the dielectric to “align” the dielectric molecules, thus “smoothing” the sound. As an engineer, I believe in impedance matching and full-coverage shields, because these things are easily proved to matter. Dielectric molecular alignment, on the other hand, is simply a fraud. The best one can say about it is that it doesn’t hurt the electrical properties of the cable.

It gets worse, however. The Sony/Philips Digital Interface (S/PDIF) standard, which defines electrical and optical interfaces for digital audio, dates back to the 1980s. Optical S/PDIF interfaces often follow Toshiba’s Toslink specification for connectors and cable, which was designed to provide error-free operation using inexpensive plastic fiber with a 1.0mm core diameter. That’s simple enough, but I saw a company at CES demonstrating Toslink cables constructed from a fiber bundle—that is, multiple independent fibers. In this case, the bundle was made to be coherent; the relative positions of each fiber were maintained from one end to the other, so the cable could actually transfer low-resolution images from one end to another, just like a medical endoscope. This technology reduces the functionality of the cable, because the bundle will capture and transmit less light than one large fiber.

I believe the high-end audio industry has developed these bizarre practices because audio technology long ago passed the point where ordinary customers could distinguish between new and old products. The tremendous improvements in sound quality achieved in the 1960s and 1970s paved the way for CD digital audio, but even that high standard was well integrated into low-cost products by the late 1980s. Diminishing returns on further investments in quality have driven the audio industry to a form of madness.

Now, here’s the payoff. Are we in the microprocessor industry at risk for the same disorder? We, at least, have customers who genuinely need all the performance we can deliver, essentially without limit. That alone guarantees Microprocessor Report a long-term future. Some computer buyers, however, are already satisfied with the speed of their systems, and I don’t know what we can offer these people to get them to upgrade. I just hope we won’t be reduced to touting snake oil and silver bullets.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

Silicon à la Carte
Max Baron - Principal Analyst  {01/12/2004}

QuickSilver’s adaptive computing machine (ACM) can dynamically reconfigure itself for efficient execution of the functions that must be delivered. The ACM aims at the best of both worlds, offering reduced silicon real estate and, at lower frequencies, lower power consumption. Its target markets are the cost-conscious and power-sensitive mobile communications, consumer, and automotive segments.

The ACM technology was initially aimed at massively parallel arrays delivering very high performance for data-intensive workloads such as multichannel video and voice processing, medical imaging, software radio, and base transceiver stations. QuickSilver’s requirement to implement connectivity among multiple types of processors has produced, however, an approach that can also be used in modest configurations.

Microprocessor Report readers can access the full story here (5 pages; 4 figures): www.mdronline.com/mpr/h/2004/0112/180201.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

ClearSpeed Hits Design Targets
Tom R. Halfhill - Senior Editor  {01/12/2004}

ClearSpeed Technology has successfully tested early production samples of its CS301 floating-point coprocessor and is delivering small quantities to prospective customers. The massively parallel chip is hitting all its design targets for clock frequency (200MHz), power consumption (less than 2W), and peak floating-point performance (25.6 GFLOPS).

In addition to offering the CS301 as a standard part, U.K.-based ClearSpeed has decided to license the processor’s synthesizable Verilog model for customers wishing to design their own chips. The model is configurable, so customers can determine the number of parallel-processing elements, the number and type of function units, and the amount of on-chip memory.

MPR visited ClearSpeed’s small U.S. office in Los Gatos, California, shortly before Christmas to observe some math-intensive software running on the CS301, which was unveiled at Microprocessor Forum 2003. (See MPR 11/17/03-01, “Floating Point Buoys ClearSpeed.”) The company has produced a small number of evaluation boards, with two CS301 chips per PCI board.

Using three of those boards and special drivers, ClearSpeed demonstrated an ordinary PC executing up to 30 GFLOPS. Although that performance is considerably less than the peak capability of 153.6 GFLOPS for six CS301 chips, it is respectable performance when all the coprocessors must share the same 133MB/s PCI bus. Production boards will allow more coprocessors per board and will have a PCI-X interface; larger systems can use any number of boards.

Unfortunately, there are no industry-standard benchmark results for the CS301 yet, mainly because ClearSpeed has been testing customer applications. Furthermore, the most popular industry-standard benchmarks are unsuitable for the CS301.

Microprocessor Report readers can access the full story here (2 pages; 1 figure): www.mdronline.com/mpr/h/2004/0112/180202.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

ARM Expands ARM11 Family
Tom R. Halfhill - Senior Editor  {01/05/2004}

Two new series of cores will join the ARM11 family in 2Q04: the ARM1156 and the ARM1176. Each series has two cores: the ARM1156T2F-S and ARM1156T2-S, and the ARM1176JZF-S and ARM1176JZ-S, respectively. All four are 32-bit synthesizable embedded-processor cores based on the progenitors of the ARM11 family, the ARM1136JF-S and ARM1136J-S, which first appeared in 2002. The parentage is significant, because MPR considers the ARM1136JF-S to be among the best in its class—which is the reason it won the MPR Analysts’ Choice Award for 2002 in the category of soft intellectual-property (IP) processor cores.

Our only concern is the rapid proliferation of ARM cores and the compromises they impose. Gone are the days when ARM offered a basic 32-bit embedded RISC processor in any color the customer wanted, as long as it was black. Today, ARM has so many different processor cores, and so many architectural extensions and enhancements, the company must churn out an increasing number of very similar cores in an attempt to offer the optimum combinations of features customers desire. Inevitably, some customers will have to settle for a suboptimal combination.

ARM could solve that problem by offering even a limited amount of configurability, following the lead of IP vendors like ARC International, MIPS Technologies, and Tensilica. Even without that flexibility, however, the ARM1156- and ARM1176-series processor cores are worthy additions to the elite ARM11 family.

Microprocessor Report readers can access the full story here (3 pages; 1 figure): www.mdronline.com/mpr/h/2004/0105/180101.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

ISSCC Promises Progress
Peter Glaskowsky - Editor-in-Chief  {01/05/2004}

Papers scheduled for presentation at the 2004 International Solid-State Circuits Conference (ISSCC), which runs February 15–19 in San Francisco, reflect the diversity of circuit-design technologies being developed to suit the growing range of electronic systems. We’ve assembled some highlights of ISSCC 2004 from the advance program published last month; following the conference,  we’ll go into more detail on some of these presentations.

Intel will talk about its Prescott design, the first 90nm member of the Pentium 4 family, and IBM will describe a 90nm implementation of the PowerPC 970, the original 130nm version of which was launched at Microprocessor Forum 2002. The ISSCC program says IBM will incorporate a feature called PowerTune for “rapid frequency and power scaling” in this new chip; this feature should allow Apple to produce PowerPC 970–based laptops to go with its PowerMac G5 desktop.

A separate Intel abstract also appears to refer to Prescott, describing logic circuits designed to operate at 7GHz in the double-clocked ALUs of a 3.5GHz chip. The abstract says low voltage-swing logic and 90nm technology were the key elements needed to permit such high-speed operation. The abstract does not report whether these ALUs are 16 bits wide, which is the case with the current 130nm Northwood Pentium 4 die, or 32 bits wide, which would better suit the rumors of 64-bit datapaths in Prescott.

A session on emerging technologies pushes the boundaries of integrated-circuit fabrication and operation. Seiko Epson will describe polymer transistors manufactured using ink-jet printing. The transistors have channels 10 microns wide and 500 microns long, and they presumably operate at very low frequencies. Superconducting circuits are also described in this session, one paper presenting a complete 8-bit microprocessor that operates at 15.2GHz, with power consumption of 1.6mW. The 5mm2 chip includes 5,000 niobium Josephson junctions. Its power efficiency is more than one thousand times better than that of conventional silicon processors.

ISSCC never fails to amaze us with new technology, and it’s clear that ISSCC 2004 will continue this tradition. For more information on ISSCC 2004, visit www.isscc.org/isscc on the Web.

Microprocessor Report readers can access the full story here (2 pages): www.mdronline.com/mpr/h/2004/0105/180102.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.