Embedded Microprocessor Watch

Issue #172 -- 03/29/2004

Editor: Tom R. Halfhill

In this issue:

Serious Power for Embedded Systems
Peter Glaskowsky - Editor-in-Chief  {03/29/2004}

Back in the old days most embedded processors were derived from Unix workstation processors. There was little ongoing development of microprocessor cores specifically for embedded systems—and most embedded systems used inexpensive microcontrollers anyway.

The rise of the Internet and of digital entertainment changed all that. Almost all today’s embedded processors were designed specifically for embedded systems. No publication has done a better job of covering this revolution than MPR, and no industry conference has hosted more announcements of key products and technologies than our Embedded Processor Forum.

EPF 2004 takes place the week of May 17 at the luxurious Fairmont Hotel in San Jose, California. Our conference program includes 20 presentations of new products for the embedded-processor industry spread across five sessions—high-performance processors, software tools, embedded signal processing, video processing, and low-power processors. (Please visit www.mdronline.com/epf04 to see the complete program.)

The processors being announced at EPF span a wide range of power and performance characteristics, from ultralow-power cores for cellphone handsets to ultrapowerful chips created for high-end networking equipment. We’re especially pleased this year to be able to offer a session on software tools, responding to an increasingly common request from Forum attendees. Every year, it becomes more difficult for system developers to take full advantage of new architectures and instruction-set extensions; at EPF04, you’ll hear about new tools meant to solve this problem.

It’s no secret that the past few years have been difficult ones for events and publications in the computer industry. We have worked hard to continue delivering the same high-quality content in every issue of MPR and at each of our conferences. You may have noticed that the February issue of MPR, at 68 pages, was the largest we’ve ever published. We’re putting the same effort into EPF, with full-day seminars to deliver the latest information on the products and technologies in this market.

On the Monday before the conference, Tom Halfhill will present an updated version of his highly popular Microprocessors for Professionals seminar. This seminar can bring anyone up to speed on the fundamentals of microprocessor design. Thursday, after the conference, our own Max Baron and former MPR analyst Jim Turley will respectively examine all the most important low-power and high-performance embedded processors. These two seminars will cover the chips and cores announced at EPF, comparing them with competing products.

EPF04 has one of the best programs we’ve ever put together, but for it to be a great conference, we need your help. We hear that many companies have again freed up their travel and training budgets. EPF is a great way to get back up to speed on all the changes that have occurred in our industry over the past few years. If you can attend only one event this year, make it the Embedded Processor Forum. We hope to see you there.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

Dial the Future
Max Baron - Principal Analyst  {03/22/2004}

Abstract
TI’s new OMAP 2 chips promise that one day, not far in the future, we’ll be able to hold everything in one hand. Announced on February 23 at the annual 3GSM conference in Cannes, France, two chips, the OMAP2410 and OMAP2420, are claiming all the desktop’s functions and then some. To be sure, these chips will not compete in performance with either a multigigahertz PC processor or with the latest high-performance, power-thirsty graphics engine; instead, the chips will enable, for the first time, integration of telephony, imaging, multimedia, and high-performance graphics for games. And if cellphones employ the chip, they will provide a single conduit for receiving and sending content.

Texas Instruments is targeting OMAP 2 architecture at 2.5G and 3G mobile phones. TI expects to help increase smartphone and camera-phone volumes by introducing new functions that can enhance the personal entertainment experience. The OMAP 2 chips will deliver functions such as prosumer-level digital-camera support, digital-camcorder capability, and interactive 3D gaming.

Microprocessor Report readers can access the full story here (3 pages; 1 table): www.mdronline.com/mpr/h/2004/0322/181201.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Intel Addresses the 64-Bit Question
Peter Glaskowsky - Editor-in-Chief  {03/15/2004}

For a company that spends billions of dollars each year on research and development, Intel had surprisingly little to say at its recent Developer Forum in San Francisco. Intel offered updates to its Itanium roadmap, talked about wireless networking, and released the first official details of its support for the AMD64 extensions to the venerable x86 instruction set. Most of the IDF presentations merely rehashed information announced at previous forums, and the conference overall failed to shed enough light on some of the company’s most critical initiatives.

The 64-bit x86 content was limited to a few words in keynote speeches. AMD was never mentioned, but Intel privately confirmed that what Intel calls Extended Memory 64 Technology is nearly identical to AMD64. (We’re working on our own detailed comparison of the AMD and Intel extensions for publication in an upcoming issue of Microprocessor Report.)

The IDF roadmap update for the Itanium processor family for 2004 shows new members that have faster cores and more cache. Fanwood will offer a 1.6GHz clock rate and 3M of on-chip L3 cache. LV Fanwood will run at 1.2GHz and has the same L3 cache size but will consume less power, due to its lower operating voltage. Both these parts will be available by the end of the year. Intel has also promised to ship a new version of its Madison processor this year, upgraded to 9M of L3 cache and a 1.7GHz clock rate.

Intel’s plans to develop liquid crystal on silicon (LCOS) display components were a highlight of IDF. Intel’s LCOS devices are chip-scale liquid-crystal displays (LCD) less than an inch across. A rear-projection television can be built from a light source, projection optics, LCOS chips, and associated control electronics. In principle, such a system can cost much less than a full-size LCD with its own drive circuitry. Intel’s proven ability to manufacture complex silicon chips in high quantity will give it instant credibility as it seeks to expand its business into this new area. We can only hope that future IDFs present an equally crisp, clear picture of Intel’s other chip-development efforts.

Microprocessor Report readers can access the full story here (3 pages; 1 table): www.mdronline.com/mpr/h/2004/0315/181101.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Xilinx Reconfigures Triscend
Tom R. Halfhill - Senior Editor  {03/15/2004}

Only weeks after ARM announced the acquisition of Triscend (see MPR 2/17/04-02, “ARM Grabs Triscend”), Xilinx loosened ARM’s grip with a higher bid and wrestled the small chip vendor away from ARM. The Xilinx deal is final, averting a further bidding war or the intercession of other suitors.

Not until April will Xilinx disclose how much money it paid to pry Triscend out of ARM’s arms, but it’s apparently more than $13.2 million, the amount of cash ARM had promised to fork over for the suddenly attractive company. As ARM had planned, Xilinx will absorb almost all 41 Triscend employees and phase out Triscend’s corporate identity.

Although Xilinx says it will continue supplying Triscend’s customers with Triscend chips, the product line will undergo significant changes. Over the next 12–24 months, Triscend’s engineering team will develop new products to support the Xilinx strategy of combining embedded-processor cores with reprogrammable logic. Both companies currently sell chips that embody that strategy, albeit with some differences.

Microprocessor Report readers can access the full story here (2 pages): www.mdronline.com/mpr/h/2004/0315/181102.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

ARC 700 Aims Higher
Tom R. Halfhill - Senior Editor  {03/08/2004}

Only a few months after introducing the ARC 600 configurable processor, ARC International has announced another new core: the ARC 700. But it’s not an egregious exercise in instant obsolescence. The new(er) ARC processor is fully compatible with its still-available predecessor and is intended for customers willing to tolerate a larger core in return for higher performance.

ARC claims the ARC 700 is the smallest 400MHz 32-bit RISC core available—one-third the size of an ARM11 when fabricated in a 0.13-micron IC process—with lower power consumption to boot. Of course, the actual mileage may vary, because the ARC 700 is a customizable processor in the ARC tradition, so the clock speed, silicon area, and power consumption greatly depend on the customer’s final configuration. Even so, it’s a safe assumption that an ASIC or SoC based on the ARC 700 will outrun a comparable chip built around the ARC 600, which peaks at about 290MHz in a 0.13-micron process. The downside is that the base configuration of the ARC 700 requires nearly four times the silicon area and power of an ARC 600, which explains why the slower core remains in the product line.

In addition to its higher potential clock frequency—mostly the result of an even deeper pipeline—the ARC 700 has several other improvements over the ARC 600: dynamic branch prediction; a faster, single-cycle adder; some DSP extensions that were previously optional; wider memory interfaces for the instruction and data caches; a nonblocking load/store pipeline that allows two hit-under-miss data accesses; out-of-order completion for nondependent instructions; and two new instructions that will be especially useful in multicore designs.

Despite all those enhancements, the ARC 700 supports the same ARCompact instruction-set architecture (ISA) as the ARC 600 and ARCtangent-A5 do, which allows programmers and compilers to mix 16- and 32-bit instructions for greater code density. In fact, the ARC 700 is binary compatible with both the ARC 600 and ARCtangent-A5, although recompilation will improve performance. In addition, the ARC 700 works with the same new hardware- and software-development tools ARC introduced last year. The ARC 700 is fully synthesizable and is licensed as soft intellectual property (IP)—and it’s available now.

Microprocessor Report readers can access the full story here (5 pages/2 graphics): www.mdronline.com/mpr/h/2004/0308/181001.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Cirrus Logic Grows Ten ARMs
Tom R. Halfhill - Senior Editor  {03/01/2004}

Encouraged by the reception of its first ARM9-based processor in 2001, Cirrus Logic is rolling out 10 more chips with an ARM920T core. All are highly integrated system-on-chip (SoC) devices with impressive features and on-chip peripherals, but the feature creep isn’t coming at a price—even the new high-end chip costs 37% less than Cirrus Logic’s first ARM9 processor from three years ago.

The new standard parts in Cirrus Logic’s Maverick family of 32-bit embedded processors range from the EP9301 at the low end to the EP9315 at the high end. In between are the EP9303, EP9304, EP9305, EP9306, EP9307, EP9309, EP9310, and EP9311. They will join the EP9312, Cirrus Logic’s first ARM9 processor, which was announced in June 2000 and shipped in early 2001.

Even at the low end of this line, the EP9301 is a well-integrated SoC with a 166MHz core and such luxuries as a 10–100Mb/s Ethernet controller, dual USB 2.0 host controllers, internal boot ROM, 12-channel DMA, 12-bit analog-to-digital converter (ADC), I2S stereo audio, and multiple timers. The higher-end models run at 200MHz and add many more features. Because all these chips use the ARM920T core, they also have 16KB instruction and data caches, Thumb-1 instructions, and an MMU. The last feature allows them to run more-sophisticated embedded operating systems, such as Linux and Windows CE.NET.

Two of the new processors are available now: the low-end EP9301 and the high-end EP9315. The latter chip is pin compatible with the existing EP9312; the others have smaller packages with reduced pin counts to cut costs. Cirrus Logic says the remaining chips will sample next quarter and ship in 3Q04. Prices for the new processors range from $8.96 to $24.01 in 10,000-unit quantities.

Microprocessor Report readers can access the full story here (4 pages/2 graphics): www.mdronline.com/mpr/h/2004/0301/180901.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

PMC’s Processors Face Reality
Markus Levy  {03/01/2004}

An increasing number of vendors are using the EEMBC benchmarks to understand the behavior of their processors, whether in the form of an IP core or of a silicon product. These benchmarks are useful for determining a first-order approximation of the way a processor will perform in a real application. Using the EEMBC benchmarks, we subjected two processors from PMC-Sierra to a series of tests that made it possible to examine their microarchitectural features. The analysis applied to the RM5261A and RM7000C can be extrapolated to provide useful data for selecting cache sizes, dual-issue processing, power requirements, and operating frequency for other RISC processors.

In the investigation, with help from Shay Gal-On of PMC-Sierra, we utilized the benchmarks in EEMBC’s networking suite to highlight the architectural differences between these two processors. For example, the Route_Lookup benchmark from EEMBC’s Networking suite fits nicely into the L1 cache of both processors, so we used it to quantify the benefits of the dual-issue capability of the RM7000C. Another EEMBC networking benchmark, PacketFlow, shows how cache size affects performance. The Open Shortest Path First (OSPF) benchmark involves a large number of pointer-handling operations, many decisions, and not a great many computations. This type of code limits the compiler’s ability to optimize.

Microprocessor Report readers can access the full story here (3 pages/4 graphics): www.mdronline.com/mpr/h/2004/0301/180902.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.