Embedded Microprocessor Watch

Issue #173 -- 04/26/2004

Editor: Tom R. Halfhill  

In this issue:

Stretching Performance
Max Baron - Principal Analyst  {04/26/2004}

The gap between ASIC and FPGA implementations has been the target of many companies, small and large, with products ranging from single high-frequency engines to structures using multiple processors in parallel.

Microprocessor startup Stretch, Inc., may have found a product to fill the gap with the introduction of its S5000 chip family, designed to offer software-configurable ISA extensions via field-programmable logic. Stretch employs a user-configurable processor (Tensilica’s Xtensa V) interfaced with on-chip programmable logic to create an off-the-shelf chip family. By offering a component, rather than intellectual property, Stretch is positioning itself to provide processors to developers that lack the budget, time, or expertise to create their own ASIC processor.

Microprocessor Report readers can access the full story here (5 pages; 3 graphics): www.mdronline.com/mpr/h/2004/0426/181701.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

IBM Loosens Up CPU Licensing
Tom R. Halfhill - Senior Editor  {04/26/2004}

IBM Microelectronics has announced some important steps toward making the PowerPC architecture more widely available as licensable intellectual property (IP) for custom chip designs. However, the much publicized “Power Everywhere” initiative still falls short of matching the flexible licensing models and customizing options from competing IP vendors.

Until last year, IBM licensed PowerPC cores only to customers that worked with IBM on their custom designs and manufactured the chips at IBM fabs. In early 2003, IBM began allowing customers to do their own design work and to manufacture the chips at other foundries. At first, only the PowerPC 405 and 440 hard cores were available for licensing under that model.

Now, IBM is relaxing things a little. Among the announcements: IBM will consider licensing any Power or PowerPC core or chip implementation, although limitations apply; IBM will allow customers to freely download a synthesizable model of the PowerPC 440 for evaluation; and IBM plans to form an open committee to help steer the future evolution of Power/PowerPC, although IBM will retain control of the architecture.

Soon after IBM’s announcements, Applied Micro Circuits Corp. (AMCC) disclosed an unprecedented licensing and acquisition agreement with IBM that hints at how far IBM is willing to go. In addition to licensing PowerPC processor cores to AMCC, IBM sold an entire line of PowerPC chips and at least one engineering team.

IBM’s grand strategy is to foster the development of a broad IP portfolio around the Power architecture. (“Power” is IBM’s umbrella term for the CPU architecture that encompasses both its Power-series server CPUs and the PowerPC architecture jointly developed with Motorola in the early 1990s.) Many press reports have confused IBM’s initiative with the open-source model that has worked so successfully with the Linux kernel, but IBM is not opening the Power architecture to that extent. Instead, a governance committee with open membership will help IBM determine the future direction of the architecture, and IBM will encourage other companies to develop complementary IP for it.

Microprocessor Report readers can access the full story here (3 pages): www.mdronline.com/mpr/h/2004/0426/181702.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Preview: Embedded Processor Forum 2004
Tom R. Halfhill - Senior Editor  {04/19/2004}

The boom years of the 1990s aren’t quite back, but at least now the semiconductor industry has a steady pulse. Embedded Processor Forum 2004 will be the coming-out party for several innovative development projects that survived the tech recession and hope to breathe new life into the embedded market. They span an unusually wide range of architectures and applications.

During the two-day conference portion of EPF 2004—May 18–19, at the Fairmont Hotel in San Jose, California—new embedded processors, architectures, and synthesizable cores will be unveiled by Altera, AMD, ARM, Cradle, Emblaze, MobilEye, Motorola, PMC-Sierra, Texas Instruments, Tensilica, Ultra Data, and VIA/Centaur. Almost all these presentations will be the first technical disclosures of their products. The new processors run the gamut from traditional RISC and CISC architectures to bold new designs optimized for communications, mobile multimedia, machine vision, and signal processing.

Each conference day will begin with a keynote address, this year featuring ARM on May 18 and AMD on May 19. A three-part session on unusual embedded-software tools is scheduled for May 18, with presentations from ACE (Associated Compiler Experts), Silicon Hive (a Philips-funded startup), and Transitive. A special panel discussion about on-chip interconnect technology will follow the regular sessions on May 19. As is customary, the first day of the conference will end with a vendor exhibition in the evening.

Three all-day seminars on May 17 and May 20 will bracket the conference portion of the forum. The Monday seminars are “Microprocessors for Professionals,” an introductory-level presentation by Tom R. Halfhill, senior analyst, In-Stat/MDR, and “Best Processors for Low-Power Applications,” presented by Max Baron, principal analyst, In-Stat/MDR. The Thursday seminar is “Choosing the Best High-Performance Embedded Microprocessors,” presented by Jim Turley, industry analyst, Silicon Insider.

For more information or to register for EPF 2004, visit www.MDRonline.com/epf04.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2004/0419/181601.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Bulverde Announced
Max Baron - Principal Analyst  {04/19/2004}

With its newly announced PXA27x processor family, formerly code-named Bulverde, Intel is taking a sober look at the PDA business and retargeting itself to address cellphones, PDAs, and other wireless applications.

Aside from the known capabilities of its XScale core, the PXA27x family introduces three additional technologies: the much talked about multimedia functions, via support of Wireless MMX; digital-camera processing; and Intel’s Wireless SpeedStep technology, borrowed from Pentium processors and partly implemented on the earlier PXA25x and PXA26x.

Microprocessor Report readers can access the full story here (2 pages/1 graphic): www.mdronline.com/mpr/h/2004/0419/181602.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

ST Chooses ARM7 for MCUs
Max Baron - Principal Analyst  {04/19/2004}

STMicroelectronics’ logical choice for its new 16-bit/32-bit microcontrollers, announced on April 12, is a core based on the ARM7 Thumb plus the software-development tools and operating systems that support it. ST’s ARM-based MCUs will target industrial-control systems, point-of-sale and vending machines, test equipment, and telecom applications such as bridges and protocol translators.

Microprocessor Report readers can access the full story here (2 pages/1 graphic): www.mdronline.com/mpr/h/2004/0419/181603.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

From the Publisher’s Desk: My First 100 Days
Frank Dickson  {04/12/2004}

It is with great pleasure that I write the first installment of “From the Publisher’s Desk.” In my short time as MPR’s publisher, I have been impressed by the dedication and attention to quality shown by every member of In-Stat/MDR’s MicroDesign Resources team. It is our goal to continue the fine tradition of Microprocessor Report and to improve our coverage. I’d like to share with you my insights after the first 100 days of my tenure.

This year promises to be a strong one. We have a substantial program planned for the Embedded Processor Forum (May 17–20), and attendance promises to be our best since 2000. We hope you can join us. Later this year, we have some surprises in store for the attendees of October’s Microprocessor Forum. Please stay tuned for news of those.

We also have some changes planned for Microprocessor Report. We will be expanding the scope of our coverage to better reflect the changing environment for microprocessors. Today’s environment is characterized by a “battle for the socket,” an ongoing war in which multiple product classes compete for board real estate. The combatants consist of ASSPs, standard or configurable CPUs, ASICs, FPGAs, and other solutions. The battlefield includes the computation, industrial, consumer, automotive telematics, and communications markets. Most of you are embroiled in this battle, so this is hardly news to you. However, our focus is to provide you with greater insights into these ongoing silicon melees. Rest assured, we will also continue our tradition of providing the industry’s leading coverage of microprocessors.

The year is also a year of change for my team: a current member is leaving, and two old friends have returned. Peter Glaskowsky has left his position as editor in chief to pursue personal interests. Peter was with MDR for almost eight years as an analyst and editor. He was a tremendous advocate for Microprocessor Report and made significant contributions to our fine coverage.

Kevin Krewell returns to us after a brief stint working at a microprocessor startup. He will assume the role of editor in chief. Kevin’s insights and leadership were missed, and we are very glad he is back.
Also returning to the In-Stat/MDR team is Jim McGregor. Jim was in the past a senior analyst covering memory for In-Stat. Now, Jim will bring a systems perspective to our team, thanks to his valuable experience at the Motorola Computer Group, On Semiconductor, and STMicroelectronics.

Finally, to all of you readers—from those who have subscribed for many years to those who only recently began subscribing—I want to say thank you for your support. We appreciate that you have entrusted us with providing you with the most timely and in-depth information on microprocessors. On behalf of all of us at MDR, I assure you we will do everything we can to continue earning your trust and providing you with the finest research in the industry.

Thank you!

To find out more about Microprocessor Report, please visit: www.mdronline.com.

Alchemy Adds Security Engine
Tom R. Halfhill - Senior Editor  {04/05/2004}

AMD’s Alchemy family of MIPS32-based embedded processors has a new member that integrates a security engine for encrypted communications. The new Au1550 supports Internet Protocol security (IPsec) and the Secure Sockets Layer (SSL) protocol for virtual private networks (VPN).

The Au1550 is the fourth, and most advanced, member of the embedded-processor family that AMD gained by acquiring Alchemy Semiconductor in 2002. It’s the first Alchemy chip to incorporate a security engine for accelerating data encryption and decryption. Instead of developing a security engine of its own, AMD licensed the SafeXcel IP engine from SafeNet, whose intellectual property, chips, boards, and software are widely used throughout the industry.

AMD designed the Au1550 for network-gateway products and network-attached storage (NAS) subsystems. Its relatively low power consumption—less than 500mW at 400MHz—makes it suitable for some mobile wireless applications as well as for power-over-Ethernet systems on wired networks. The chip is sampling now and is scheduled for production in 2Q04.

Microprocessor Report readers can access the full story here (3 pages/2 graphics): www.mdronline.com/mpr/h/2004/0405/181401.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

EZchip Adds New NPU Line
Peter Glaskowsky - Editor-in-Chief  {04/05/2004}

When EZchip introduced its first network processor (NPU) in 2002, that processor gained immediate attention for its fast, flexible architecture and low system cost. The NP-1 was the market’s first NPU to support full-duplex operation on 10Gb/s networks, and, for its routing address tables, it used relatively inexpensive DRAM instead of the expensive content-addressable memories some other NPUs require. The subsequent NP-1c moved this design to IBM’s CU-11 110nm fabrication process, allowing an increase in clock speed and a lower manufacturing cost. The NP-1c entered volume production in December 2003.

EZchip has now announced the first two members of its NP-2 family of network processors, scheduled to begin sampling in 4Q04. These devices will be built in TSMC’s 130nm process, and they have significantly greater integration. The NP-2e has a 10Gb/s NPU core that is software compatible with the NP-1c, plus two traffic-management coprocessors; 10 Ethernet media access controllers (MAC) that operate at 1Gb/s; one 10Gb/s Ethernet MAC; and one SPI-4.2 interface, compatible with a wide range of 10Gb/s switch-fabric chips and coprocessors from other companies. This chip will sell for $595. The $795 NP-2s will add another SPI-4.2 interface to support OC-192 rates with up to 192 STS-1 channels.

EZchip says that in 2005 it will add other members to the NP-2 family—including a device with TCP (Transmission Control Protocol) and security-processing engines. The company claims more than 30 “paying customers” for its NP-1 products, an excellent showing for a young company in such a competitive market. The new NP-2 chips are likely to attract just as much attention.

To find out more about Microprocessor Report, please visit: www.mdronline.com.