Embedded Microprocessor Watch

Issue #174 -- 05/31/2004

Editor: Tom R. Halfhill  

In this issue:

Tensilica Tackles Bottlenecks
Tom R. Halfhill - Senior Editor  {05/31/2004}

Rarely has the ascendance of embedded processors been more evident than at the recent Embedded Processor Forum, where several companies announced products and features that must seem like tantalizing fantasies to the architects of staid PC processors. One company in particular, Tensilica, is continuing to pursue a farsighted corporate vision of architectural flexibility and automated design.

At EPF 2004, Tensilica announced new versions of its configurable microprocessor core and optional DSP engine, which are licensed as soft intellectual property (IP). When combined with the company’s previously announced VLIW-like instruction extensions and next-generation development tools, they will redefine the possibilities for embedded processors.

The new Xtensa LX is a major upgrade of Tensilica’s existing configurable processor core, the Xtensa V. Xtensa LX tackles three challenges vexing today’s CPU architects: the architectural limitations on compute efficiency, the bottlenecks on I/O bandwidth, and rising power consumption. For SoC developers, Xtensa LX preserves the advantages of a customizable CPU architecture while laying the groundwork for future development tools that will further automate the task of creating an optimized SoC design.

Tensilica also announced at EPF a new configurable DSP engine called Vectra LX. Designed specifically for the Xtensa LX processor—Tensilica already offers a DSP engine for earlier Xtensa cores—Vectra LX uses 64-bit instruction words containing three issue slots for ALU, multiply-accumulate, and load/store operations. In all, Vectra LX supports about 200 instructions for 16-bit fixed-point signal processing. Vectra LX is included with Xtensa LX and adds a level of DSP performance unprecedented in a synthesizable RISC processor.

All this probably seems too good to be true. However, Tensilica can back up its claims with independently certified benchmark results. Xtensa LX clobbers every other benchmarked processor in its class—and even some processors out of its class. For instance, in the EEMBC consumer suite, Xtensa LX achieved the highest out-of-the-box ConsumerMark score ever recorded by a licensable CPU core: 171.6 when simulated at 330MHz. That’s more than three times higher than the previous out-of-the-box champ, the Philips TriMedia TM5250, which scored a ConsumerMark of 51.3 when simulated at 500MHz.

Tensilica also submitted Xtensa LX to Berkeley Design Technology Inc. for DSP benchmarking. Result: an optimized Xtensa LX core and Vectra LX DSP engine, simulated at 370MHz, easily outran every other licensable DSP or CPU core ever tested by BDTI. Xtensa LX scored a BDTIsimMark2000 of 6,150—about 70% higher than the previous champ, the CEVA-X1620 DSP, which was simulated at 450MHz.

To achieve these extraordinary benchmark results with a small RISC processor, Tensilica has introduced some groundbreaking new technology and development tools. We believe it’s only a matter of time before Tensilica’s approach to configurability and design automation exerts more influence over the whole industry.

Microprocessor Report readers can access the full story (7 pages; 3 graphics) here: www.mdronline.com/mpr/h/2004/0531/182201.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

ARM Opens Up to SMP
Kevin Krewell - Senior Editor  {05/24/2004}

We can now safely say that the future of high-performance processing—whether it is PCs, servers, or embedded processing—will be multicore and multithreaded processors. ARM has embraced that future with its first symmetric multiprocessing licensable core. ARM’s MPCore supports one to four ARMv6-compliant processors combined with multi-CPU-optimized cache-coherency logic and interrupt controller. For now, ARM is satisfied that up to four CPUs will offer enough scalability. The market demand for performance scaling through multiple processors comes from the consumer and networking markets, where there are often concurrent datastreams that can be processed simultaneously.

Multicore solutions are beginning to spring up everywhere. Although this is not a new concept (a number of dual MIPS solutions ship today), ARM’s approach is unique in that the multicore architecture is wrapped in such a way that, in an SoC design, it appears to the other IP blocks to be a monolithic processor.

MPCore also adds another dimension in power management. ARM, in its alliance with National Semiconductor, has incorporated a power-management scheme, IEM, that controls power over the whole core in active state, using multiple voltage and frequency steps. With the addition of multicore, adaptive shutdown states allow varying levels of individual core shutdown.

Using TSMC’s CL013G 130nm process with typical silicon, ARM expects the full-out power of a four-CPU MPCore implementation to be 3.3mW/MHz, with the potential frequency range of 335–550MHz. With a very realistic size of 32K for the instruction and data caches, no vector floating-point unit, and 128 interrupts, a dual-CPU implementation should take 19mm2, and a four-CPU design should fit 35mm2, using the TSMC 130nm process.

Microprocessor Report readers can access the full story (4 pages, 4 graphics) here: www.mdronline.com/mpr/h/2004/0524/182101.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

StarCore DSPs Boost VoIP
Tom R. Halfhill - Senior Editor  {05/18/2004}

Two decades of deregulation have slashed the cost of long-distance phone calls to pennies a minute, but even pennies aren’t free. Business and residential customers eager for lower-cost alternatives are eyeing voice-over-Internet-Protocol (VoIP) telephony, which piggybacks digitized voice packets onto existing Internet services. Result: talk gets even cheaper.

The compound annual growth rate of the IP-telephony market is about 35% for residential users and about 53% for business users, according to Norm Bogen, director of networking market analysis at In-Stat/MDR. To feed that growing market, Freescale Semiconductor—Motorola’s former semiconductor group—is introducing a new family of five DSPs based on the StarCore VLIW architecture.

Although Freescale’s new MSC711x-series DSPs are useful for any 16-bit fixed-point signal processing, they are especially suited for packet telephony. Two of the chips have Ethernet media-access controllers, and all have time-division multiplexers, DDR memory controllers, 32-channel DMA, and generous amounts of on-chip SRAM. The DSPs are designed to work in tandem with Freescale’s PowerQuicc communications processors, but they will function as slaves to virtually any host processor via an Ethernet connection or their 8/16-bit host data interface (HDI).

In an interesting departure, all five of the new DSPs are designed around the SC1400 synthesizable DSP core licensed from StarCore LLC, an independent offshoot of Infineon, Lucent/Agere, and Motorola. (See the sidebar, “StarCore LLC Offers Soft DSPs,” in MPR 10/20/03-01, “Motorola Enhances StarCore DSP.”) Previous Motorola DSPs—including other StarCore-based devices from Motorola—have been full-custom hand-packed designs. Freescale says the synthesizable SC1400 core, which accelerated the design project, allows the company to rapidly create additional variations, provides better portability across different fabrication processes, and sacrifices a negligible amount of performance versus a hard core.

Members of the MSC711x family are priced relatively low for high-performance DSPs having their integrated features, ranging from about $12 for the MSC7110 to about $24 for the MSC7116, in 10,000-unit volumes. They are mutually pin compatible and are binary compatible with software written for MSC81xx-series StarCore DSPs. Samples of the chips will be available this summer, with production scheduled to begin in November and December.

Microprocessor Report readers can access the full story (5 pages, 3 graphics) here: www.mdronline.com/mpr/h/2004/0518/182001.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Risk Reduction Faraday Style
Max Baron - Principal Analyst  {05/18/2004}

Most leading vendors of embedded processors tend to keep under wraps, as long as they can, the details that make their chips work, so it is refreshing to see Faraday taking the opposite approach. Its FA626 ARM v4 core, announced a few weeks ago, and the technology on which it is based are communicated in detail to the world at large, not just to the few prospective licensers associated with the huge corporations leading the communications and networking markets.

Faraday’s brainchild is not your usual processor core, which leaves the expense and risk of interfacing, caching, and core-to-core communication to the design engineer. The FA626 goes a few steps further, since it’s being delivered with its own on-chip interconnect, L2 cache, and coherency logic configured to support additional processing resources. As if these functions alone were not enough, the FA626 also exposes the ARM coprocessor interface, to which the company can help designers connect their processor or accelerator of choice.

Faraday’s target market is “maximum SOC-MIPS, ARM popularity,” which implies that the company hopes to use the popularity of the ARM architecture and its available software development tools to go after applications such as network communications and video, today populated by MIPS and PowerPC engines.

Microprocessor Report readers can access the full story (4 pages, 4 graphics) here: www.mdronline.com/mpr/h/2004/0518/182002.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

VIA Embeds Its Security Strategy
Kevin Krewell - Senior Editor  {05/18/2004}

At Embedded Processor Forum 2004, Glenn Henry, founder and president of VIA’s Centaur Division, updated the company’s processor roadmap and announced additional features on the company’s 90nm processor with improved security processing and media processing. The newest version of the 90nm processor will maintain the “Esther” code-name announced at Microprocessor Forum 2003.

The new C5J processor just completed tape-out in a 90nm IBM SOI, low-k dielectric process. The chip will be only 31.7mm2 and has 26.2 million transistors; samples are expected in 4Q04. The die size is a bit smaller than the 33mm2 that Henry projected at MPF03, and the die is smaller than that for any previous Centaur design. With the smaller die size, the C5J should be cost-effective to manufacture, despite using the more expensive IBM process, but costs will depend on the yields of the state-of-the-art IBM process. The new chip will also add Intel’s SSE2 and a full hardware implementation of SSE3 instructions. VIA added SSE3 on the basis of public information Intel released on the new instructions.

In addition to higher clock frequencies, the C5J will also get a performance boost over its 130nm predecessor, Nehemiah/C5P, from a faster front-side bus and a larger L2 cache. The bus is Centaur’s first implementation of the Intel Pentium M bus and will support a 200MHz base clock and quad-pumped data transfers. The L2 cache was doubled from the 64K, 16-way cache on Nehemiah to the 128K, 32-way version on Esther.

Microprocessor Report readers can access the full story (3 pages, 4 graphics) here: www.mdronline.com/mpr/h/2004/0518/182003.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Reconfigurable “Illogic”
Rich Belgard  {05/10/2004}

Having read Tredennick and Shimamoto’s “point” to this “counterpoint,” I am truly amazed at the naïveté these experienced and bright designers have shown. For at least a decade, some people have been predicting that “reconfigurable logic” will supplant the microprocessor. I think the prediction of the death of the microprocessor is unfounded. I think there is a place for reconfigurable logic—and the place is in addition to, or as an extension to, the microprocessor.

The conclusion of “Microprocessor Sunset” is that microprocessors will no longer be capable of handling the new age of applications—according to the authors, untethered systems.

Fittingly, I am writing this counterpoint on a new Intel ULV-Pentium M laptop, somewhere over Kansas. Weighing around three pounds, my laptop says I have about 4.5 hours of battery left. I wouldn’t even want to guess what battery life I’d have if I were running, on the same silicon, not XP Pro but Word under DOS. Oh, and on this particular trip, my Blackberry has been powered-on for the past three days, receiving my email and stock quotes, and still is at 85% battery life. (And yes, the radio is off only for the flight.) I have my trusty cell phone with me, and its battery lasts about a week, if I am circumspect. Each of these untethered devices uses at least one microprocessor.

So, I find it quite strange that “Sunset” suggests I will need to throw out everything I know, and everything our industry knows, and change the entire paradigm to reconfigurable systems.

Microprocessor Report readers can access the full story (3+ pages) here: www.mdronline.com/mpr/h/2004/0510/181901.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Freescale Secures PowerQuicc
Tom R. Halfhill - Senior Editor  {05/10/2004}

Freescale Semiconductor—the newborn spinoff from Motorola—has introduced a new PowerQuicc II Pro family of communications processors and two new members of the PowerQuicc III family. In all, there are eight new PowerQuicc chips. The most significant improvements over existing PowerQuicc processors are higher-performance CPU cores, faster memory systems, enhanced network interfaces, and integrated security engines for encrypting and decrypting data packets.

The integrated security engines are optional, so customers can still choose to use external security coprocessors or software-based security—or to not implement packet security at all, as export-control regulations sometimes require. Although the new processors aren’t the first PowerQuicc chips to integrate security hardware, their security engines are more advanced than those in existing PowerQuicc chips.

In addition, the new PowerQuicc processors will deliver greater overall performance, thanks to faster DDR memory systems and enhanced PowerPC cores running at higher clock frequencies. Clock rates will receive an even bigger boost when production moves from the current 0.13-micron fabrication process to the next-generation 90nm process, probably in late 2005 or early 2006.

Freescale’s roadmap for the PowerQuicc line shows a transition to four PowerPC cores: the e300, e500, e600, and e700. By surrounding these cores with different combinations of on-chip peripherals and I/O interfaces, Freescale plans to offer a PowerQuicc family for almost every conceivable communications application. The overall trend is toward higher performance on all fronts: CPUs, memory systems, peripheral I/O, and network connections. In addition, Freescale will create PowerQuicc-based semicustom designs for customers that want something a little different.

All eight new PowerQuicc chips are scheduled to begin sampling later this year. Production quantities of the PowerQuicc III chips should be available in 4Q04, and production of PowerQuicc II Pro chips will follow in 1H05.

Microprocessor Report readers can access the full story (5 pages; 2 graphics) here: www.mdronline.com/mpr/h/2004/0510/181902.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

The Only Constant Is Change
Kevin Krewell - Senior Editor  {05/10/2004}

Those of you who have been paying close attention and who read my last editorial must be wondering why I’m writing this one. My last editorial was my supposed swan song at In-Stat/MDR and Microprocessor Report. Well, after almost four months at a startup, I’m back, and I’m editor in chief of Microprocessor Report. My return is a good news/bad news story. The good news (for me at least) is that I’m glad to be back at In-Stat/MDR and writing for Microprocessor Report. It’s also another opportunity to contribute to the microprocessor community in the best way I know how. The bad news is that my return is due to the departure of Peter Glaskowsky. Peter was a long-time and valued contributor to MDR, and he will be missed here.

I consider being Microprocessor Report’s editor in chief a great honor and a great responsibility. I was recently talking to the CEO of a major Silicon Valley chip company and he told me how much he values the in-depth and impartial content of Microprocessor Report and that he reads it on a regular basis, mostly on planes. (In fact, MPR seems to be the reading material of choice for many subscribers on airline trips. Maybe we should publish airline schedules in the report for even greater utility.)

My goal is to make our content even more relevant as the microprocessor industry tackles the challenges of complex system-on-chip (SoC) designs, 90nm and smaller geometries, intellectual property (IP) use and reuse, the rise of untethered computing, and many other issues. This is a very dynamic industry, and MDR must change to continue to be of value to it.

Over the next few months you can expect to see some changes here. But we will not lose our staunch independence and objectivity, although they will not prevent us from getting excited when we find a company or product or technology we think is really significant.

Some of these changes will be seen at the Embedded Processor Forum, which is fast approaching as I write this. Because microprocessors do not work without software, we have an EPF04 session on software technologies that includes an intriguing presentation from Transitive Technology, which claims its software will allow any processor to run instructions from another instruction set.

We also recognize that the embedded market (except for most x86 processors) has moved to SoC designs, and that connecting the various cores on the die is as significant a challenge as designing the cores themselves. At EPF04, on Wednesday afternoon, we have a panel covering on-chip buses, addressing both licensable IP and proprietary solutions. Chip designers must decide where to invest their limited resources in designing interfaces and when they would be better off licensing existing technology. Much like the trade-off SoC designers face with IP cores, the system bus can be licensed, or it can be designed in house. But the system bus is often even more critical, because, as the backbone of the SoC processor, it must connect various IP blocks and, ideally, should be scalable for the future. The panel will be moderated by a new addition to MDR’s staff but a returning veteran of In-Stat, Jim McGregor. Jim brings additional systems expertise to MDR as well as having an established background in research.

I will be opening EPF04 and moderating the Tuesday session on high-performance embedded processors. We will have presentations from ARM, Motorola/Freescale, PMC-Sierra, and VIA. As usual, we have representatives from all the key embedded instruction set architectures and most of the important vendors. I hope to see you there.

I’m very excited to be back at MDR and Microprocessor Report, and I hope I can count on you, our readers, for your continued support. I also hope we can tap into your collective wisdom and knowledge to help make this newsletter an essential part of your business.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

Microprocessor Sunset
Nick Tredennick and Brion Shimamoto  {05/03/2004}

Semiconductors have been a great business; the industry has seen the equivalent of 14% growth for the past 40 years. No other industry matches that. The integrated circuit, Moore’s law, and the personal computer were a great beginning. But we’re at the end of the beginning with the value PC, the value transistor, and the decline in semiconductor-process adoption rates.

This article describes how the industry arrived at value PCs and at value transistors, and it discusses the consequences. To put the conclusion up front, the market is shifting from tethered systems (plugged into the wall for power) to untethered systems. As it shifts, the engineering goal is changing from cost-performance to cost-performance-per-watt. However, today’s microprocessors and DSPs cannot satisfy the combined performance and power requirements of untethered systems. ASICs are too expensive. Programmable logic devices are too slow and too expensive. Current memory components—DRAM, SRAM, and flash memory—are unsuitable. Faster transistors burn less active power, but in two process shrinks, their leakage currents rise by an order of magnitude—not a good thing for untethered systems.

In other words, we can’t get there just by shrinking the components we have.

The situation seems to be a problem with no solution, but the industry is about to emerge from a 30-year stall in the improvement of design methods that was caused by our preoccupation with the microprocessor. The solution is reconfigurable systems combined with a new nonvolatile memory cell.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2004/0503/181801.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

In the Viewfinder: TI’s Camera Chips
Max Baron - Principal Analyst  {05/03/2004}

With so many OEMs pouring digital cameras into the market, the market segment is now even more attractive for Texas Instruments and is consistent with the surge of activity seen in the consumer-electronics space. Texas Instruments, already working very hard to continue and increase its dominant market share in cellphones, announced in fall 2000 its first-generation single-chip camera-on-chip, the TMS320DSC21. This device was followed by this year’s recent introduction of the high-performance TMS320DM320 chip, which brings TI’s offering close to the high-end requirements of prosumer digital cameras. Additionally, an image engine created in cooperation with HP was announced in February at the Photo Marketing Association’s trade show in Las Vegas.

Microprocessor Report readers can access the full story here: www.mdronline.com/mpr/h/2004/0503/181802.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.