Processor Watch

Issue #176 -- 06/28/2004

Editor: Tom R. Halfhill  

In this issue:

Interconnects Target SoC Design
Jim McGregor -    {06/28/2004}

For more than 10 years, interconnects between chips, circuit boards, and systems have taken center stage, because technology has not kept pace with increasing microprocessor speed and bandwidth requirements. These interconnects have become major bottlenecks in overall system performance. However, the same advances in semiconductor manufacturing that have enabled faster microprocessors are also enabling the combination of multiple functions on a single chip, using tens of millions to hundreds of millions of transistors, thus overcoming the limitations of chip, board, and system interconnects. These complex system-on-chip (SoC) designs force the interconnects between the functional blocks to become critical design elements, driving overall design, timeline, and cost. Consequently, a number of licensed off-the-shelf intellectual-property (IP) interconnect solutions have become available, to address this need.

Licensable interconnects are offered by ARM, IBM, Sonics, CrossBow Technologies, and Fulcrum Microsystems.  AMBA (ARM), CoreConnect (IBM), and Smart Interconnect IP (Sonics) are multiple-bus architectures that combine a system bus and peripheral bus.  CoreConnect also includes a register bus and Smart Interconnect IP includes an integrated memory scheduler. Xfabric (CrossBow) and Nexus (Fulcrum) are switch fabrics architectures used as on-chip interconnects. All the interconnects offer advantages, but vary according to flexibility, size, layout, power, performance, latency, core type, tools, cache coherency, standards, market adoption, and cost. AMBA and CoreConnect are offered license free and royalty free to promote other products or services from ARM and IBM.  The remaining architectures are offered in some form of license fee plus royalty or NRE fess.
 
No one-size-fits-all interconnect exists for silicon. The best solution is to analyze the key requirements of the design and select the solution or solutions meeting those requirements. The bus architectures of AMBA, CoreConnect, and Smart Interconnect IP offer solutions that optimize the interfaces according to the requirements of the functional blocks, such as those for processors and peripherals. The switch architectures of Nexus and Xfabric offer the performance and scalability required for a very high performance configuration. In terms of low up-front fees, tool support, vendor support, and industry adoption, AMBA has the lead, but it is often tied to a processor core from ARM, just as CoreConnect is tied to IBM. In terms of market presence, AMBA and CoreConnect are the most popular solutions, but many companies are showing interest in Smart Interconnect IP.  At this time, Nexus and Xfabric have no announced designs, but both have indicated they are working with several customers.

Microprocessor Report readers can access the full story (7 pages, 7 graphics) here: www.mdronline.com/mpr/h/2004/0628/182603.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Altera’s New CPU for FPGAs
Tom R. Halfhill - Senior Editor  {06/28/2004}

Some trends are hard to ignore, like coffee cups getting larger than coffee pots and telephones getting smaller than mouths. More to the point, the cost of spinning a custom chip in standard silicon is soaring, while the prices of FPGAs keep declining. FGPA vendors love this, because the argument for implementing a custom design in programmable logic becomes more compelling every year.

To lure designers away from the clutches of foundries, FPGA vendor Altera took the stage at the recent Embedded Processor Forum and introduced Nios II, a second-generation family of 32-bit synthesizable RISC processors. All Nios II cores are intended primarily for integration into system-on-programmable-chip (SoPC) devices—essentially, SoCs in FPGAs. However, they are also suitable for structured ASICs and regular SoCs, especially as a migration path from FPGAs if production volumes climb.

The first three members of the Nios II family are the Nios II/f (fast), Nios II/s (standard), and Nios II/e (economy). They are basically the same processor core with minor variations. Don’t, however, confuse Nios II with Nios 2.0, the second version of Altera’s original Nios soft processor for Excalibur FPGAs. (See MPR 12/3/01-01, “Excalibur Sharpened By Nios 2.0.”) Nios II is an entirely new design that isn’t binary-compatible with the older Nios architecture.

At the top of the Nios II family is the full-featured Nios II/f, which has a six-stage pipeline, dynamic branch prediction, a single-cycle 32-bit multiplier, a single-cycle barrel shifter, and optional instruction/data caches. To save gates, the other Nios II cores do without some of these features. The Nios II/s shortens the pipeline from six stages to five, substitutes static branch prediction for dynamic prediction, omits the data cache, and increases the latency of the 32-bit multiplier and barrel shifter from one clock cycle to three.

The economy-model Nios II/e is even sparser. It drops the 32-bit multiplier, the barrel shifter, the branch predictor, and both the instruction cache and data cache. It also has a “pipeline” that is, in effect, only one stage long. Actually, the pipeline has six stages, but it can process only one instruction at a time, so it’s effectively unpipelined.

Despite its parsimony, Nios II is hardly the Yugo of processor cores. One outstanding feature of the architecture is an extendable instruction set, something more commonly associated with the configurable processors from ARC International, MIPS Technologies, and Tensilica. Designers can add up to 256 custom instructions to a Nios II processor, and programmers can use the instructions in assembly language or C/C++ functions. In contrast, the previous Nios 2.0 architecture allowed designers to add only five custom instructions.

Microprocessor Report readers can access the full story (6 pages, 4 graphics) here: www.mdronline.com/mpr/h/2004/0628/182602.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

The New, New MDR
Kevin Krewell - Senior Editor  {06/28/2004}

My last editorial was titled “The Only Constant is Change.” So it is in our industry, and so it must be in our publication. An abiding passion for the dynamic microprocessor business drives our readers, and it drives us to continue following the industry. And because the microprocessor industry and the information industry keep changing, we too will change. Our corporate owners want to see more subscribers and increased attendance at our forums. Those indicators are less frequent feedback points, however, so I am also asking you, our readers, for more timely feedback on our present content and on the format plans I’m about to reveal.

The most important change we plan for Microprocessor Report is that we will provide additional analysis in our stories, including a specific, deep “cover-story” article each month. We believe our monthly average page count will remain roughly the same, but the weekly online posting of stories may become less regular. There may be weeks in which we have stories in process but don’t have a competed story. Fundamentally, the newsletter was never about news but about the context of that news. There are plenty of free websites you can go to for basic speeds and feeds and for the official corporate statements. Our report needs to provide the news within the context of competitors, larger industry trends, and market changes. To do so takes more time, and, unfortunately, we frequently are not briefed more than a week in advance.

The in-depth stories may not be tied to a particular announcement but rather to a significant issue in the industry. We may also call upon more outside contributions from recognized authorities in areas in which we are not expert. We also recognize that traditional microarchitecture has become less critical as system-on-chip (SoC) designs proliferate. The areas of semiconductor process development and tool chains are becoming more integrated into the microprocessor design decisions. The problems the industry faces in complexity, process problems like leakage and lagging transistor interconnect speeds, and probabilistic circuit behavior are changing the way high-performance microprocessors are built. The race for higher frequency and deeper pipelines led to dead-end processors that were too hot and too power-hungry. A different design paradigm, one that balances performance and power, is rising today. Intel recently made it official that multicore processors are the future of PC and notebook designs. Another design challenge will be the addition of more performance into portable devices while still maintaining or increasing battery life.

Getting the Stories Out
I’d like to take you for a quick tour of our story process. The analysts first spend one to three weeks doing the research, conducting interviews, and writing the story. We then submit the first draft of the story for our editorial board’s review, for vendor review, and for peer review. During the following week, the author integrates the various reviewers’ feedback. In the week preceding publication, our copy editor finalizes the language and makes the style consistent with MDR style, and our production staff converts the final version into HTML and PDF formats. As you can see, the production process usually requires more than three weeks. Our process takes a lot longer than that of newspapers and news websites, but the end product is a more thoughtful, accurate, and definitive analysis of an announcement or industry trend. From time to time, we do take shortcuts to get stories out sooner, but these are largely simple stories that need little, if any, review. These shortened stories do not allow in-depth analysis, however, and we found we were doing too many of them. Such quick stories do not provide the value you expect from our premium newsletter.

For quick coverage of announcements, we are creating new section called Chip Watch. It will replace Resources and will be updated as needed. Chip Watch will have a format similar to that of Patent Watch, with a short list containing the company name, product name, date announced, and key speeds, feeds, and features.

We also plan changes to our twice-yearly forums. Although Embedded Processor Forum and Microprocessor Forum have each had its own unique identity, at times that identity got in the way of having the best and most timely content. To give the forums more flexibility, we are renaming them Fall Processor Forum and Spring Processor Forum. We needed a name that still conveyed the content and the heritage. Many people had come to associate Microprocessor Forum with PC and server processors only, even though more than half the content concerned embedded devices. The Embedded Processor Forum name was very clear, but it prevented us from including PC and server processors. The new names give us the flexibility to bring the best content twice a year. We are also planning to have our first forum in Taiwan later in October based on the material presented at the Fall Processor Forum.

These are some changes you will be seeing very soon. We also plan to make some of our data, like those from our chart watches, available for download. To cover system issues, we’ve added Jim McGregor to our staff, and he will be hosting an additional Electronic Design Forum, co-located with the Fall Processor Forum.  For more information on the new Electronic Design Forum, see more our web site at www.mdronline.com/edf04/.

We have planned these changes to make our newsletter your essential read and to make our forums more relevant and timely. I welcome your feedback. You can reach me at Kevin.Krewell@reedbusiness.com.

To find out more about Microprocessor Report, please visit: www.mdronline.com.

ARC 700 Secrets Revealed
Tom R. Halfhill - Senior Editor  {06/21/2004}

Challenging ARM in the embedded-processor market is as daunting as challenging Intel in the PC market: you’re cruisin’ for a bruisin’. No wonder ARC International wanted to delay revealing everything about its new ARC 700 processor core until a marketing plan was in place. As ARC recently disclosed at Embedded Processor Forum 2004, the ARC 700 has additional features that directly challenge ARM’s most popular processor cores.

Microprocessor Report covered the ARC 700 in depth earlier this year, detailing its new seven-stage pipeline, higher clock speeds, DSP instructions, dynamic branch prediction, wider cache interfaces, single-cycle adder, nonblocking load/store pipeline, out-of-order completion, and new support for multicore SoCs. (See MPR 3/8/04-01, “ARC 700 Aims Higher.”) Those features alone justify the ARC 700’s ground-up redesign. At EPF, ARC further revealed that the ARC 700 is the company’s first processor capable of running Linux and other sophisticated embedded operating systems. The reason: it’s the first ARC processor with a memory-management unit (MMU), translation lookaside buffer (TLB), precise exception model, and multiple privilege levels.

Virtual memory, precise exceptions, and the ability to segregate kernel-level code from user-level tasks are critical features in higher-end embedded processors. Without those features, a processor can run a variety of real-time operating systems, but it cannot run the most powerful operating systems for advanced embedded applications. Adding those capabilities to the ARC 700 makes it more suitable for the role of a host processor in networking equipment, communications infrastructures, and consumer electronics. It also puts the ARC 700 in direct competition with similar processor cores from ARM and MIPS Technologies. For the first time, ARC is breaking out of the deeply embedded market and going head-to-head against the best 32-bit processors from its most formidable competitors.

ARC says the first release of an embedded Linux for the ARC 700 will be available in July, though the company hasn’t yet announced the vendor. The first release is being ported with GNU software-development tools. GNU C isn’t as optimized for the ARC 700 as ARC’s own MetaWare tools, so a second release—recompiled with the MetaWare tools—is scheduled for later this year.

Microprocessor Report readers can access the full story (5+ pages, 3 graphics) here: www.mdronline.com/mpr/h/2004/0621/182501.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

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