Processor Watch

Issue #177 -- 07/15/2004

Editor: Tom R. Halfhill

In this issue:

Tensilica’s Automaton Arrives
Tom R. Halfhill - Senior Editor  {07/12/2004}

What’s even faster and cheaper than outsourcing a design project to India? Answer: outsourcing it to a robot. Or, actually, to a new processor design tool that automatically generates application-specific custom instructions by analyzing software written in plain-Jane C/C++.

On July 7, Tensilica announced that its long-anticipated XPRES (Xtensa PRocessor Extension Synthesis) tool will ship in 3Q04. A seat license will cost $100,000 and requires an Xtensa LX processor license, which starts at $550,000. XPRES works only with the new Xtensa LX core (see MPR 5/31/04-01, “Tensilica Tackles Bottlenecks”), not with the previous-generation Xtensa V core, which remains available. Instead, Tensilica hints that XPRES may be compatible with a future “economy model” Xtensa processor that lacks all the fancy features of Xtensa LX.

Microprocessor Report first covered XPRES after Tensilica disclosed the then-unnamed technology at Embedded Processor Forum 2003. (See MPR 6/23/03-01, “Tensilica’s Software Makes Hardware.”) After a detailed analysis, we concluded that XPRES was a significant innovation, with the potential to dramatically accelerate SoC projects.

We still feel that way. It’s not just that XPRES can automatically generate custom hardware from C/C++ code, a focus of widespread research and development. Rather, it’s the whole tool chain and design flow that sets Tensilica’s technology apart. Tensilica is closer than any other company to realizing a vision of software-driven automated hardware design that for decades has mesmerized engineers, academic researchers, and entrepreneurs.

Moreover, Tensilica automates one of the most time-consuming parts of a project: grinding out line after line of register-transfer-level (RTL) hardware descriptions for application-specific logic. XPRES can outstrip all that effort in minutes. The other tedious phase of a project—verifying the new logic—also contracts, because Tensilica Instruction Extension (TIE) language is a correct-by-construction language that’s supposed to make a faulty design impossible. XPRES frees people for the real brainwork, such as specifying the design, writing better software, and making the design trade-offs that will distinguish the product in the marketplace.

Microprocessor Report readers can access the full story (5 pages, 5 graphics) here: www.mdronline.com/mpr/h/2004/0712/182801.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

MPU EDA to Face Complexity
Max Baron - Principal Analyst  {07/12/2004}

At the 41st Digital Automation Conference, on June 8 in San Diego, keynote speaker Pat Gelsinger, Intel senior VP and CTO, reassured the audience that Moore’s Law is alive and well and will continue to provide increasing numbers of transistors for at least ten more years.

Designs, according to Gelsinger, will change not only method but also scope: future chip-global optimizations across multiple constraining variables will replace local optimizations involving only one or two variables.

Microprocessor Report readers can access the full story (1+ pages) here: www.mdronline.com/mpr/h/2004/0712/182802.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

AMD vs. Intel in Dual-Core Duel
Kevin Krewell - Senior Editor  {07/06/2004}

On June 13, 2004, AMD responded to the dual-core processor strategy Intel revealed in May. AMD’s new roadmap is more cautious than Intel’s plan. AMD will use dual cores in server and high-end desktop processors, but it is making no immediate commitment to the mainstream desktop and mobile markets. We do not expect AMD’s newly announced Sempron brand for lower-end “value” PCs to include dual-core processors, at least in the near term.

AMD plans to launch its dual-core server processor in mid-2005 and its dual-core high-end desktop processor in 2H05, so the chips will almost certainly be produced in the company’s 90nm SOI process. Revenue shipments of 90nm products are scheduled to begin in 3Q04, so the fabrication process should be mature by mid-2005. AMD revealed new roadmap details and said the first dual-core design had reached tapeout. The company undoubtedly timed its announcement to steal some thunder from Intel’s launch of the new Grantsdale chip set, LGA775 socket, Pentium 4 processors, and processor rating system.

At one time, AMD’s new dual-core processor may have been code-named K9, but the company appears to be distancing itself from generational names. For one thing, “K9” sounds like a dog. More important, the microarchitectures of AMD’s (and Intel’s) new processors may not change much as the engineers refocus on multicore designs and tweaks to reduce power consumption.

AMD will stick to the 940-pin socket for Opteron through most of 2005 and introduce the dual-core processor in that socket. AMD wants long-term stability for the Opteron platform. However, this consistency will prevent AMD from using DDRII (DDR2) memory with Opteron, which includes the memory controller and interface on the processor die. Server platforms evolve at a more deliberate pace than do desktop platforms, so delaying adoption of DDRII should not be a crippling disadvantage for AMD, because Opteron’s integrated memory controller already reduces the latency of the memory system. By 2006, however, AMD will have to move to DDRII memory and a new socket.

Microprocessor Report readers can access the full story (4 pages, 5 graphics) here: www.mdronline.com/mpr/h/2004/0706/182701.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

Intel Launches Grantsdale Chipset
Jim McGregor -    {07/06/2004}

As part of its Digital Home initiative, Intel launched a new chipset to support its Prescott version of the Pentium 4 microprocessors for desktop PCs. The code names for the new chipset family are Grantsdale and Alderwood, but the family will appear in the Intel line as the 915P/G and 925X.

The most prominent feature of the new chipset family, broadly known as Grantsdale, is support for PCI Express (PCIe) peripherals and graphics, shifting away from the older and slower PCI and AGP interfaces. Grantsdale is the first chipset on the market to support PCIe and DDR2, a faster memory interface. Other features of Grantsdale include the Intel Graphics Media Accelerator 900 (GMA 900) for the 915G (the “G” denotes graphics); Intel High Definition Audio (HD Audio); Intel Matrix Storage Technology (RAID); and Intel Wireless Connect Technology (Wi-Fi). Grantsdale and the new LGA-775 socket will also lay the groundwork for future performance enhancements to the Pentium 4 platform.

Grantsdale changes the PC architecture through the introduction of PCIe and DDR2, which will increase the performance of PCs. In addition, Grantsdale improves the home and business user experience with enhancements in graphics, audio, and storage combined with an optional Wi-Fi solution. List pricing in 1,000-unit quantities is $50 for the 925X, $41 for the 915G, and $37 for the 915P in conjunction with the ICH6 south bridge. South bridges supporting RAID (ICH6R), Wi-Fi (ICH6W), or RAID and Wi-Fi (ICH6RW) are available for an additional cost. All chipset configurations are in production and available in quantity.

Microprocessor Report readers can access the full story (4+ pages, 3 graphics) here: www.mdronline.com/mpr/h/2004/0706/182702.html. To find out more about Microprocessor Report, please visit: www.mdronline.com.

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